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Explorer
Explorer
253 Views
Registered: ‎03-27-2017

IP Integrator Auto Reverts Port Width

I'm trying to change the input port width of the vio IP in my block design - everytime I change it to a larger bitwidth and proceed to synthesis, the port width changes back to its original single bit value.

It seems the parameter is not being changed in the source files for the IP block. I'm wondering how to fix this issue?

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4 Replies
Moderator
Moderator
212 Views
Registered: ‎01-16-2013

Re: IP Integrator Auto Reverts Port Width

@bfung 

 

In settings-->Project Settings-->IP, Try to clear the cache or you can use the below TCL command to clear IP cache:

config_ip_cache -clear_output_repo 

 

After this reset and regenerate the IP output products. Also, try recreating the HDL wrapper of Block design.

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Xilinx Employee
Xilinx Employee
198 Views
Registered: ‎02-14-2014

Re: IP Integrator Auto Reverts Port Width

Hi @bfung ,

The problem here is with the flow which you're following. You are changing port width inside IP which is correctly reflected at the input pin of IP.

But since you are not changing width of input port which is made external, when you save and validate block design, the port with of IP gets changed back to port width of external port (which is expected).

Correct flow should be - 

1. Modify input port width inside IP.

2. Delete external port associated with your modified port.

3. Make the corresponding port external again.

So as an example, if I am changing port width of probe_in0 port from 1 to 4, correct tcl commands for this operation would be -

startgroup
set_property -dict [list CONFIG.C_PROBE_IN0_WIDTH {4}] [get_bd_cells vio_0]
endgroup
delete_bd_objs [get_bd_nets probe_in0_0_1] [get_bd_ports probe_in0_0]
startgroup
make_bd_pins_external [get_bd_pins vio_0/probe_in0]
endgroup
save_bd_design
validate_bd_design

Regards,
Ashish
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Explorer
Explorer
162 Views
Registered: ‎03-27-2017

Re: IP Integrator Auto Reverts Port Width

@syedz Unfortunately this does not resolve the problem of the probe width reverting back to a single bit

@ashishd I have not made any ports external - I am just referring to the probe input port of the VIO IP block in the block design

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Moderator
Moderator
142 Views
Registered: ‎01-16-2013

Re: IP Integrator Auto Reverts Port Width

@bfung 

 

Can you share the BD tcl file (write_bd_tcl) to reproduce the issue at our end. Also share the snapshots or steps you are following in changing the width of the port

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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