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Observer jamesba-bbc
Observer
5,591 Views
Registered: ‎07-27-2011

IP Packager Producing Strange Results

I've been trying to package up some vhdl as an IP package using Vivado's IP packaging features.  The code is entirely written in vhdl, and should be relatively simple to package, however when I create the IP package I've encountered a number of problems:

 

  • Regardless of what I do all the configurable paramaters are greyed out and unusable when I instantiate the IP Core in another design. How do I make them useable?
  • When I instantiate the IP in another design it seems to have decided that all the .vhd and .xdc files are verilog headers, which is clearly wrong.

I also get a question mark next to several of my AXI stream interfaces when instantiating in IP Integrater. I have no idea what that means and nothing happens if I click on this question mark.

 

Any help would be appreciated.

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2 Replies
Observer jamesba-bbc
Observer
5,589 Views
Registered: ‎07-27-2011

Re: IP Packager Producing Strange Results

Further examination shows that the verilog include issue is due to me misunderstanding what the "include file" checkbox was for.

 

The greayed-out configuration seems to happen if I try to use a list of key-value pairs for configuring the parameter, but not if I let it be a free entry integer value.

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Xilinx Employee
Xilinx Employee
5,575 Views
Registered: ‎09-20-2012

Re: IP Packager Producing Strange Results

Hi,

 

I just gave a try to recreate your problem. I have used "Value Validation list" for giving specific set of values to parameter and packaged the IP.

 

I didnot see any issue when customizing the created IP.

 

What is the "Value format" of the parameter?

 

Also while packaging the IP are there any warnings?

 

One small point to note, the values in the "Value validation list" should be given as below ("",):

"2","3","4"

Thanks,
Deepika.
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