07-15-2017 02:29 AM - edited 07-15-2017 03:57 AM
I have packaged a custom IP which may (or may not) contain some blocks, in this case CDC synchronisation units depending on IP settings. For example if user ticks a "Asynchronous regs" option in my IP it will generate some blocks named U0/cdc/wsync_reg.
I have also packaged the _clocks.xdc file which contains "set_max_delay" timing constraints for this block - in the same way how Xilinx FIFO IP does.
The problem is that when IP user doesn't use this "Asynchronous regs" option, the CDC blocks are not synthesized, but the XDC file still has timing contraints for them, which generates a lot of "Critical Warning: no cells matched ..." messages during implementation.
Is there a way to work around this?
I know I can't use conditional expression like 'if' in XDC files. So I have two alternatives:
1. Use a TCL file - _clocks.tcl. But I saw people complaining that constraint scoping doesn't work for TCL files.
2. Relevant 'set_max_delay' lines in _clocks.xdc should be generated or deleted at IP configuration time. Again in similar way that I see some Xilinx IPs do. But I have no idea if/how I can do that.
07-22-2017 05:49 AM
07-26-2017 02:49 PM
Bump, I am running into exactly the same problem.
Anyone have ideas?