UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
1,442 Views
Registered: ‎06-21-2017

IP Packager can't infer port widths

Jump to solution

I have a design that contains an AXI interface.  I wish to use IP packager so that I can drop the design into a couple Zynq devices.  Since the design is still in development, the number of registers on that AXI bus may change.  To this end, the address width is defined in a package file as follows:

 

Constant AXI_32b_REGISTERS       : integer   := 32;
Constant USABLE_AXI_ADDR_WIDTH   : integer   := integer(ceil(log2(real(AXI_32b_REGISTERS)))); -- number of address bits --needed to uniquely address AXI_32b_REGISTERS
Constant C_S_AXI_ADDR_WIDTH       : integer    := USABLE_AXI_ADDR_WIDTH+2; -- add two to allow for byte addressing

 

The design synthesizes and the schematic tells me that both the read address and write address are 7 bits as they should be.  IP Packager fails with these messages:

 

  • [IP_Flow 19-627] Port 's00_axi_awaddr': XPath expression failed: Undefined parameter "C_S_AXI_ADDR_WIDTH" used in expression "(C_S_AXI_ADDR_WIDTH - 1)".
  • [IP_Flow 19-627] Port 's00_axi_araddr': XPath expression failed: Undefined parameter "C_S_AXI_ADDR_WIDTH" used in expression "(C_S_AXI_ADDR_WIDTH - 1)".
  • [IP_Flow 19-627] Address Block 'reg0': XPath expression failed: Undefined parameter "C_S_AXI_ADDR_WIDTH" used in expression "pow(2,(C_S_AXI_ADDR_WIDTH - 1) + 1)".

So what gives?  The synthesis tool knows how wide the port is, why doesn't IP packager?  The work around is easy enough.  I can just define the top level ports explicitly along with the requisite snide comment about why the parameterized version didn't work.  I just wanted to know why one tool can figure out the port width and one could not.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar brimdavis
Scholar
2,169 Views
Registered: ‎04-26-2012

Re: IP Packager can't infer port widths

Jump to solution

@bruce_karaffa "So what gives?  The synthesis tool knows how wide the port is, why doesn't IP packager?"

Welcome to the wonderful world of Xilinx's IP {dis}Integrator.

It appears to me[1] that IP packager 'scrapes' the top level source code with an ad-hoc parser, which does not actually understand VHDL.

As a result, any generic and port expressions must be explicit and entirely self contained, nor does the fun stop there:
   - constants and functions defined in a package are not allowed in generic and port expressions
   - simple stuff, like an ( others => '0' ) initial value for a std_logic_vector generic, doesn't work
   - real generics, supported in ISE XPS, are not supported by Vivado IPI
   - port types are limited to plain-old-Verilog equivalents- no user defined types, records, etc.
   - OOC is bottom-up only, meaning all IP parameters must be hard-coded at the lower levels of the hierarchy
   - packaging System Verilog or VHDL-2008 is verboten

There is a lightly documented TCL based "XPATH" mechanism for calculating dynamic port widths and values in the TCL IP wrapper code, search UG1118 for "XPATH" and "enablement expression".

-Brian

 

EDIT: clarified and added more UG1118 page references
[1] Given the horrid documentation for IP packager, it is difficult to tell for sure what Xilinx is doing.

    In contrast with Vivado IPI, the older ISE XPS provided the "Platform Specification Format Reference Manual", defining all the requisite IP declarations, file formats, and directory structure needed to create an XPS pcore IP:
      https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf

    Vivado provides us this gem from UG1118: "There are inference rules which assist in packaging the IP correctly."
    See 'Packaging a Specified Directory', page 37-39 of UG1118:
      https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug1118-vivado-creating-packaging-custom-ip.pdf
    Pages 11-12 discuss language and port restrictions.
    Pages 13-15 discuss port name inference rules.

 

 

3 Replies
Highlighted
Scholar brimdavis
Scholar
2,170 Views
Registered: ‎04-26-2012

Re: IP Packager can't infer port widths

Jump to solution

@bruce_karaffa "So what gives?  The synthesis tool knows how wide the port is, why doesn't IP packager?"

Welcome to the wonderful world of Xilinx's IP {dis}Integrator.

It appears to me[1] that IP packager 'scrapes' the top level source code with an ad-hoc parser, which does not actually understand VHDL.

As a result, any generic and port expressions must be explicit and entirely self contained, nor does the fun stop there:
   - constants and functions defined in a package are not allowed in generic and port expressions
   - simple stuff, like an ( others => '0' ) initial value for a std_logic_vector generic, doesn't work
   - real generics, supported in ISE XPS, are not supported by Vivado IPI
   - port types are limited to plain-old-Verilog equivalents- no user defined types, records, etc.
   - OOC is bottom-up only, meaning all IP parameters must be hard-coded at the lower levels of the hierarchy
   - packaging System Verilog or VHDL-2008 is verboten

There is a lightly documented TCL based "XPATH" mechanism for calculating dynamic port widths and values in the TCL IP wrapper code, search UG1118 for "XPATH" and "enablement expression".

-Brian

 

EDIT: clarified and added more UG1118 page references
[1] Given the horrid documentation for IP packager, it is difficult to tell for sure what Xilinx is doing.

    In contrast with Vivado IPI, the older ISE XPS provided the "Platform Specification Format Reference Manual", defining all the requisite IP declarations, file formats, and directory structure needed to create an XPS pcore IP:
      https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf

    Vivado provides us this gem from UG1118: "There are inference rules which assist in packaging the IP correctly."
    See 'Packaging a Specified Directory', page 37-39 of UG1118:
      https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug1118-vivado-creating-packaging-custom-ip.pdf
    Pages 11-12 discuss language and port restrictions.
    Pages 13-15 discuss port name inference rules.

 

 

1,324 Views
Registered: ‎06-21-2017

Re: IP Packager can't infer port widths

Jump to solution

Since I was prompted by the Community Mailer, and since I don't expect to get the answer that I really want "Yeah, we know this is a problem and we will fix it the next release", I accepted your solution. 

0 Kudos
Scholar brimdavis
Scholar
1,286 Views
Registered: ‎04-26-2012

Re: IP Packager can't infer port widths

Jump to solution

@bruce_karaffa "since I don't expect to get the answer that I really want <snip> I accepted your solution."

 

That was more of a list-of-problems-I've-encountered-with-IPI, rather than a solution, but thanks!

 

The only 'solution' I've found is to avoid IP {dis}Integrator whenever possible. The auto-interface-stitching and address assignment of AXI IP was useful in the older ISE XPS, but in Vivado IPI I find that the persistent limitations, bugs, and Xilinx-IP-upgrade-death-march with each new Xilinx release to be more of a headache than a benefit.

 

-Brian

0 Kudos