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Explorer
Explorer
9,523 Views
Registered: ‎08-18-2011

IP-XACT files from IP Packager contains absolute file reference

I have an IP project under revision control.

 

when the component.xml file is generated  there is a xilinx tag of

 

 <xilinx:tag xilinx:name="Vendor:Library:Name:Version_ARCHIVE_LOCATION">C:/FPGA/[absolute path to project]</xilinx:tag>

 

Is there a reason why this cannot have a relative path? This prevents this project being portable between machines.

 

The tag is generated when ipx::save_core is run i think.

 

 

Edit: Vivado 2014.4 both Windows 7 and SLED11

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Xilinx Employee
Xilinx Employee
9,517 Views
Registered: ‎09-20-2012

Re: IP-XACT files from IP Packager contains absolute file reference

Hi,

 

Do you see any errors when using the IP created on one machine on another machine?

 

Thanks.

Deepika.

Thanks,
Deepika.
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Explorer
Explorer
9,507 Views
Registered: ‎08-18-2011

Re: IP-XACT files from IP Packager contains absolute file reference

I get a message that says top level ports cannot be found for the component
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Xilinx Employee
Xilinx Employee
9,506 Views
Registered: ‎09-20-2012

Re: IP-XACT files from IP Packager contains absolute file reference

Hi,

 

Can you post the complete error message please?

 

Do you see this error after creating the IP on new machine?

 

Are you able to create the IP on the old machine without errors?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Explorer
Explorer
9,496 Views
Registered: ‎08-18-2011

Re: IP-XACT files from IP Packager contains absolute file reference

INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'ca_CPRI_Dual_Lane'...
ERROR: [IP_Flow 19-137] Could not find top-level ports for IP instance 'ca_CPRI_Dual_Lane'.
INFO: [IP_Flow 19-3500] Reset failed 'Synthesis' target for IP 'ca_CPRI_Dual_Lane'.
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'ca_CPRI_Dual_Lane'. Failed to generate 'VHDL Synthesis Wrapper' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'ca_CPRI_Dual_Lane'. Failed to generate 'VHDL Synthesis Wrapper' outputs:
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Explorer
Explorer
9,495 Views
Registered: ‎08-18-2011

Re: IP-XACT files from IP Packager contains absolute file reference

If I repackage on the new machine the build runs fine
building on the original machine has no issues
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Explorer
Explorer
9,475 Views
Registered: ‎08-18-2011

Re: IP-XACT files from IP Packager contains absolute file reference

It seems that when the IP revision goes up, the upgrade process in the outer project fixes this issue.

is there a way to tell vivado to upgrade IP even when the ip catalog revision is the same [like a refresh]
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Xilinx Employee
Xilinx Employee
9,473 Views
Registered: ‎09-20-2012

Re: IP-XACT files from IP Packager contains absolute file reference

Hi,

 

Referesh the IP repository and regenerate IP output products.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Explorer
Explorer
9,461 Views
Registered: ‎08-18-2011

Re: IP-XACT files from IP Packager contains absolute file reference

Refresh and regenerate has the same results

Which file is Vivado looking for when it says

ERROR: [IP_Flow 19-137] Could not find top-level ports for IP instance 'ca_CPRI_Dual_Lane'.

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