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IP based block design using vivado in xc7a35t

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Posts: 18
Registered: ‎12-15-2017
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IP based block design using vivado in xc7a35t

Is it necessary to use Microblaze (or Zinq) block for all designs? If I have the verilog code for my logic, can I make itself as an IP block and program the fpga through block design method???


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Moderator
Posts: 959
Registered: ‎09-15-2016

Re: IP based block design using vivado in xc7a35t

Hi @abdulrasheed1981

 

>>If I have the verilog code for my logic, can I make itself as an IP block and program the fpga through block design method???

 

Yes, you can package your verilog code to make it as a custom IP and hence then add the IP to the Block diagram as it will be present as user IP in  IP catalog.

You can also directly add the verilog module to the BD by right clicking the module in the design source hierarchy and clicking option "Add module to block design".

Well! both the methods have their pros and con, so you can take a call which method you going to use after referring below link, page 178:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug994-vivado-ip-subsystems.pdf

 

For information on creating and packaging the custom IP, refer link below:

https://china.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1118-vivado-creating-packaging-custom-ip.pdf

 

Regards

Rohit

 

 

Regards
Rohit
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Scholar
Posts: 2,841
Registered: ‎04-26-2015

Re: IP based block design using vivado in xc7a35t

You can't use the Zynq block at all in an Artix-7 (the Zynq block only works on the Zynq chips). You do not need to use MicroBlaze either; you can definitely just make the Verilog code into an IP core (or multiple cores) and put those on the FPGA directly.

Moderator
Posts: 3,776
Registered: ‎11-09-2015

Re: IP based block design using vivado in xc7a35t

[ Edited ]

Hi @abdulrasheed1981,

 

And yes you can use IPI just to integrate IPs without using a processor.

 

Note: In the latest version of vivado, with you verilog file included in your project, you can use add module feature to add you verilog file to a BD without packaging it as an ip

 

Regards,

Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Don't forget to reply, kudo, and accept as solution.
Moderator
Posts: 959
Registered: ‎09-15-2016

Re: IP based block design using vivado in xc7a35t

Hi @abdulrasheed1981

 

>>If I have the verilog code for my logic, can I make itself as an IP block and program the fpga through block design method???

 

Yes, you can package your verilog code to make it as a custom IP and hence then add the IP to the Block diagram as it will be present as user IP in  IP catalog.

You can also directly add the verilog module to the BD by right clicking the module in the design source hierarchy and clicking option "Add module to block design".

Well! both the methods have their pros and con, so you can take a call which method you going to use after referring below link, page 178:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug994-vivado-ip-subsystems.pdf

 

For information on creating and packaging the custom IP, refer link below:

https://china.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1118-vivado-creating-packaging-custom-ip.pdf

 

Regards

Rohit

 

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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