05-09-2019 07:42 AM
Vivado 2015.4, running under Windows 7 64 bit.
I have a design which was originally generated from a tcl script, but is now used in Project Mode.
3 IP blocks use the same Analog Devices domain crossing file, up_xfer_cntrl.v. There is a constraint file associated with the up_xfer_cntrl.v file, called
ad_axi_ip_constr.xdc. The xdc file is packaged with each IP.
All IP blocks are synthesised globally (i.e. OOC is not selected).
The problem is, during implementation, the constraints file is only being applied to one of the 3 IP blocks, and timing fails.
After synthesis, Edit Timing Constraints shows the following:
The constraints have been referenced to the 3 blocks as expected.
During implementation, the runme.log file shows:
INFO: [Vivado 12-1425] Replacing existing reference 'system_axi_hdmi_core_0' with 'system_axi_ad9144_core_0' for the XDC constraint: e:/... .../ip/common/ad_axi_ip_constr.xdc
INFO: [Vivado 12-1425] Replacing existing reference 'system_axi_ad9144_core_0' with 'system_axi_ad9680_core_0' for the XDC constraint: e:/... .../ip/common/ad_axi_ip_constr.xdc
After implementation, Edit Timing Constraints shows the following:
Only the ad9680_core has been constrained.
Timing fails. Paths that should be false paths in the ad9144_core block are being analysed, and failing.
Points to note:
Within each IP block, the ad_axi_ip_constr.xdc has USED_IN_SYNTHESIS and USED_IN_IMPLEMENATION ticked, in source file properties.
The PROCESSING_ORDER is set to LATE.
The SCOPED_TO_REF is set to the appropriate reference, e.g. system_axi_hdmi_core_0.
It used to work OK, in that all IP blocks were constrained correctly. Then after a change to a different, unrelated, IP block, it started failing timing.
Similar problem seen with different project, using Vivado 2016.2.
05-09-2019 07:52 PM
05-10-2019 01:13 AM
Not sure I understand what you are asking me.
.xci files are generated in \sources_1\bd\system\ip\system_axi_ad9144_core_0\ etc. There are no dcp files in this area.
As I said each IP has synthesis set to Global following Edit in Packager.
05-14-2019 03:28 AM
Is anyone from Xilinx looking at this?
Can anyone confirm whether changing from Non Project to Project flow is valid?
05-14-2019 03:53 AM
Hi @xilinx_bj_1905 ,
Please check Avrumw post, from below link:
Hope that answer your query.
05-14-2019 09:29 AM
I read the Design Flows Overview doc, UG892, referenced from the link, and I do not see anywhere it says you can not run up a Non Project flow project and then save it as a Project flow project. Indeed this is hinted at in the last comment on the link:
I did read however that some tcl commands are specific to the flow, e.g. add_files vs read_vhdl etc. The project was originally built up from a tcl script. The project was then saved and the .xpr file used as the starting point for the next design iteration. The Project flow was followed this way for many interations of the design, without issue. After one change, this "Replacing existing reference" problem appeared.
There must be something in a GUI window or report file that I can check to see where the problem is. I just need someone to guide me to it.
Bear in mind that the constraints are being applied to files within packaged IP blocks. Some of the IP blocks haven't changed in a long time.
What causes Vivado to generate the following message?
INFO: [Vivado 12-1425] Replacing existing reference 'system_axi_hdmi_core_0' with 'system_axi_ad9144_core_0' for the XDC constraint: e:/... .../ip/common/ad_axi_ip_constr.xdc.
05-16-2019 11:57 PM
I ran the design from the script (where it applies the constraints correctly and passes timing). I then checked the constraint compile order. Most of the constraints pulled through from IP blocks had the PROCESSING_ORDER column marked EARLY. I then reran synthesis and checked the compile order again. This time some of the IP constraints had PROCESSING_ORDER marked LATE and hence now came after the EARLY and NORMAL constraints.
I edited each IP block to change the constraint file PROCESSING_ORDER to EARLY. After updating the modified IP blocks, and rerunning synthesis and implementation, timing now passes. Looking in 'Edit Timing Constraints' in implemented design shows the constraint file scoped correctly to all 3 IP blocks.
The original script did not specify a setting for PROCESSING_ORDER. It didn't need to, as it is the order the files are added to the initial project that determines their order of use. Somehow the files were later given the value LATE. Not sure where/how this happened. Also not sure why being processed LATE caused the constraints to not be scoped correctly.
06-11-2019 03:22 AM
Spoke too soon. Problem not fixed. Constraints not applied to IP blocks following latest design changes. Can someone please advise what else to check for?
Why is Vivado giving the following message in Implementation log:
INFO: [Vivado 12-1425] Replacing existing reference 'system_axi_hdmi_core_0' with 'system_axi_ad9144_core_0' for the XDC constraint: .... projects/daq2/zc706/daq2_zc706.srcs/sources_1/bd/system/ip/common/ad_axi_ip_constr.xdc