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Newbie
Newbie
5,659 Views
Registered: ‎08-05-2016

IP floating point AXI4, V7.1

Hi,
I am using VHDL in Vivado 2016.2 for controlling purposes in my project. I need to generate some IP floating point for several math functions.
I haven't tried before to design IP floating point AXI, as you may know, every input or output has Tvalid when you create IP, my problem is, I do not know how to treat Tvalid signal?! Shall I give '1' or '0' or signal? Any support, explanation or clarification
I will appreciate
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Xilinx Employee
Xilinx Employee
5,645 Views
Registered: ‎08-01-2008

you can xilinx floating point operator IP . This IPs supports AXI interface. To understand the tvalid behavior

1. Refer floating point operator product guide
http://www.xilinx.com/support/documentation/ip_documentation/floating_point/v7_0/pg060-floating-point.pdf

2. You can generate the core simulate with demo_tb. check the assertion and de- assertion of axi signals

3. check AXI reference guide
http://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf
Thanks and Regards
Balkrishan
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Teacher
Teacher
5,398 Views
Registered: ‎03-31-2012

there are ways of configuring the FP IP. The easiest way is to configure it with no back pressure which is similar to "native" mode. In this case you can connect tvalid to 1, ignore tready signal and just count the latency cycles manually.
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Newbie
Newbie
5,395 Views
Registered: ‎08-05-2016

Thank you guys, thanks muzaffer that is what I have done and it works
Thanks
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