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364 Views
Registered: ‎04-30-2019

IP generation produces different outputs in project vs non-project flow

Hi there,

I've configured a Microblaze MCS subsystem in a Project based flow and tested this on the VCU108 board.  I have since tried moving to a Tcl based non-project flow and have an issue I'm not sure how to fix.  The issue seems to be that with the same XCI file, I get different LMB BRAM configs in the two flows.

I've attached my XCI file and a log from the run but what I've noticed is that the original XCI and BD files are being modified by the flow.  I've copied the 'git status' following generation below.

Why is this happening and how do I stop it?

Shareef.

        modified:   bd_0/bd_fc5c_0.bd
        modified:   bd_0/ip/ip_0/bd_fc5c_0_microblaze_I_0.xci
        modified:   bd_0/ip/ip_0/bd_fc5c_0_microblaze_I_0.xml
        modified:   bd_0/ip/ip_1/bd_fc5c_0_rst_0_0.xci
        modified:   bd_0/ip/ip_1/bd_fc5c_0_rst_0_0.xml
        modified:   bd_0/ip/ip_2/bd_fc5c_0_ilmb_0.xci
        modified:   bd_0/ip/ip_2/bd_fc5c_0_ilmb_0.xml
        modified:   bd_0/ip/ip_3/bd_fc5c_0_dlmb_0.xci
        modified:   bd_0/ip/ip_3/bd_fc5c_0_dlmb_0.xml
        modified:   bd_0/ip/ip_4/bd_fc5c_0_dlmb_cntlr_0.xci
        modified:   bd_0/ip/ip_4/bd_fc5c_0_dlmb_cntlr_0.xml
        modified:   bd_0/ip/ip_5/bd_fc5c_0_ilmb_cntlr_0.xci
        modified:   bd_0/ip/ip_5/bd_fc5c_0_ilmb_cntlr_0.xml
        modified:   bd_0/ip/ip_6/bd_fc5c_0_lmb_bram_I_0.xci
        modified:   bd_0/ip/ip_6/bd_fc5c_0_lmb_bram_I_0.xml
        modified:   bd_0/ip/ip_7/bd_fc5c_0_mdm_0_0.xci
        modified:   bd_0/ip/ip_7/bd_fc5c_0_mdm_0_0.xml
        modified:   bd_0/ip/ip_8/bd_fc5c_0_xlconcat_0_0.xci
        modified:   bd_0/ip/ip_8/bd_fc5c_0_xlconcat_0_0.xml
        modified:   bd_0/ip/ip_9/bd_fc5c_0_iomodule_0_0.xci
        modified:   bd_0/ip/ip_9/bd_fc5c_0_iomodule_0_0.xml
        modified:   microblaze_mcs_0.xml

 

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13 Replies
Xilinx Employee
Xilinx Employee
321 Views
Registered: ‎05-14-2008

Re: IP generation produces different outputs in project vs non-project flow

It is possible that the .xci and .xml file being modified but with some irrelevent content to the IP function such as path information.

But the BRAM configs should not be different with the two flow.

Would you elaborate the difference in BRAM config?

Have you tried to compare the two .xci file before and after the change?

-vivian

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Scholar drjohnsmith
Scholar
314 Views
Registered: ‎07-09-2009

Re: IP generation produces different outputs in project vs non-project flow

Modified can also mean , the file has had its time / date stamp changed.

used to be called "touched" in CVS days.

part of the make system, ensuring that the correct files get taken into account,

 

I wonder if the actual content has changed,

 

As for different final implimentations.

 

Thats expected.

   The tools have many mechonisums for optimisation,

     all they do is meet your timming constraints and stop.

 

Its quiet concevable, esspecialy if you have out of context , that different cores finish being synthesised at different times on different runs, resulting in different builds.

 

let alone the artificial aneealing that they say is no longer present, but we seem to get different outputs on different runs on different machines. All meet timming, and work , but different.

 

Its interesting , but is it a problem to you ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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306 Views
Registered: ‎04-30-2019

Re: IP generation produces different outputs in project vs non-project flow

@drjohnsmith The whole point of the IP flow is that you can regenerate exactly the same output in every project.

@viviany The top level XCI files are identical before and after running but some of the BD XCI files are modified.  Below is a diff of one of the BD files that is modified and it shows the change in MEM_SIZE.

I've also attached the full diff from all the bd_0 files.

diff --git a/vivado/ip/microblaze_mcs_0/bd_0/ip/ip_6/bd_fc5c_0_lmb_bram_I_0.xci b/vivado/ip/microblaze_mcs_0/bd_0/ip/ip_6/bd_fc5c_0_lmb_bram_I_0.xci
index 65691b0..40f3fe1 100644
--- a/vivado/ip/microblaze_mcs_0/bd_0/ip/ip_6/bd_fc5c_0_lmb_bram_I_0.xci
+++ b/vivado/ip/microblaze_mcs_0/bd_0/ip/ip_6/bd_fc5c_0_lmb_bram_I_0.xci
@@ -74,16 +74,16 @@
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">BRAM_CTRL</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">131072</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:configurableElementValue> 

 

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295 Views
Registered: ‎04-30-2019

Re: IP generation produces different outputs in project vs non-project flow

OK, this seems to be a bug in synth_ip.  I've created an alternate flow when I run the triple read_ip/generate_target/synth_ip which works as expected.  In UG896 it seems to state that there's no need to run generate_target before running synth_ip but this is either incorrect or there's a bug in 2018.3.

Thanks.

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Scholar drjohnsmith
Scholar
283 Views
Registered: ‎07-09-2009

Re: IP generation produces different outputs in project vs non-project flow

Its a common missconception. The point of IP is not to get exactly down to the BEL the same desing each time.

     Unless you put constraints on where things can be placed / routed this is never going to happen.

Also, the tools require to be able to optimise any IP into your desing. All the tools are doing is meeting your constraints, so unless you contrain to use exactly the same BEL etc, they will not.

This is especialy true if you change which chip the IP is going into ,

Just marking a route thats is trouble as not critical is a way to get a design to pass synthsis , but unless you knwo / document why you can do the change, and the impacts, not a way to get a desing to work inpractise.

Imagine comming back to this in a years time,

    will you or anyone else knwo why the constraint has been set ?

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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274 Views
Registered: ‎04-30-2019

Re: IP generation produces different outputs in project vs non-project flow

@drjohnsmith Thanks for your opinion but you're not helping here.  From your last point I'm assuming you've misunderstood the issue at hand.

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225 Views
Registered: ‎04-30-2019

Re: IP generation produces different outputs in project vs non-project flow

@viviany , can you confirm you've taken some action out of this post?  How are users supposed to raise bugs on Xilinx with only a forum to access?

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Xilinx Employee
Xilinx Employee
203 Views
Registered: ‎05-14-2008

Re: IP generation produces different outputs in project vs non-project flow

How did you generate your tcl script to run the non-project flow?

There is a "CONFIG.MEMSIZE" option in the tcl command to create the bd cell.

What is the value of this option in your tcl script?

-vivian

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Don’t forget to reply, kudo, and accept as solution.
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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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196 Views
Registered: ‎04-30-2019

Re: IP generation produces different outputs in project vs non-project flow

The Tcl files are generate by the IP Catalog generator.  Surely this is quite clearly a bug.  I've got 3 data points,

1.  The IP is successfully generated when using the GUI in a Project Flow.

2.  It doesn't work if you use read_ip/synth_ip in a Non-Project Flow.

3.  It does work if you use read_ip/generate_target/synth_ip in a Non-Project Flow.

Point 2 above is detailed as valid in your documentation.

 

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175 Views
Registered: ‎04-30-2019

Re: IP generation produces different outputs in project vs non-project flow

@viviany bump

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Xilinx Employee
Xilinx Employee
151 Views
Registered: ‎05-14-2008

Re: IP generation produces different outputs in project vs non-project flow

Would you attatch your tcl script?

We need to reproduce the issue for further investigation.

-vivian

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Don’t forget to reply, kudo, and accept as solution.
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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Highlighted
137 Views
Registered: ‎04-30-2019

Re: IP generation produces different outputs in project vs non-project flow

There's a testcase in the first post of the thread. 

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70 Views
Registered: ‎04-30-2019

Re: IP generation produces different outputs in project vs non-project flow

@viviany any update on this?

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