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Visitor andrejt
Visitor
7,887 Views
Registered: ‎10-11-2013

IP packager BRAM interface

I have a custom IP and I try to package signals for one BRAM port. In the IP packager I select

bram_rtl interaface, master mode, and when mapping ports, the tool allows mapping of the

data ports in the oposite direction: data output from IP maps to logical name DIN and vice versa.

 

I belive this results in wrong data connections when using the IP in the IP integrator - the IP is

connected to one BRAM port of Block Memory Generator. When I observe the generated output

products (VDHL file), the data connections are wrong. The IP works fine if I manually connect

the individual signals, but I would like to use the interface.

 

  Andrej

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6 Replies
Xilinx Employee
Xilinx Employee
7,885 Views
Registered: ‎07-11-2011

Re: IP packager BRAM interface

Hi,

 

I have a custom IP and I try to package signals for one BRAM port. In the IP packager I select

bram_rtl interaface, master mode, and when mapping ports, the tool allows mapping of the

data ports in the oposite direction: data output from IP maps to logical name DIN and vice versa.

 

Can you share screenshots for better understanding please ?

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Visitor andrejt
Visitor
7,880 Views
Registered: ‎10-11-2013

Re: IP packager BRAM interface

The left image is my interface setup in IP packager: note BRAM_dinb (IP input port) mapped to DOUT and

BRAM_doutb (IP data output port) mapped to DIN.

 

The right image is manual signal connection, which works OK, but it doesnt work if I connect using the interface.

 

    Andrej

 

 

 

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Visitor andrejt
Visitor
7,851 Views
Registered: ‎10-11-2013

Re: IP packager BRAM interface

I did some further experiments. If I manually edit the xml file produced by the IP packager and change

the logical mapping of the data ports: BRAM_dinb to logical DIN

 

<spirit:portMap>
  <spirit:logicalPort>
     <spirit:name>DIN</spirit:name>
  </spirit:logicalPort>
  <spirit:physicalPort>
      <spirit:name>BRAM_dinb</spirit:name>
  </spirit:physicalPort>

 

and change BRAM_doutb to logical DOUT it solves my problem !

I can use the IP interfaces to connect my IP to the blk_mem_gen instance and it works fine.

 

Summary: when using the IP packager for BRAM interface, the packager forced me to swap data ports

(which is presumably correct for this type of connection), but when using the IP in the IP integrator,

the ports are automatically switched again, producing the wrong connections.

 

I still dont know if this is a bug in Vivado 2013.2 or is there some other option I am not aware about,

since I cannot find specific documentation about using interfaces.


  Andrej

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Adventurer
Adventurer
5,712 Views
Registered: ‎03-05-2008

Re: IP packager BRAM interface

Hi all,

 

Does anyone know if there has been a proper resoution to this anomaly? An answer record perhaps.

 

I'd like to use a BRAM interface on my own custom IP. At the moment I have the individual address, data, write enable etc lines all wired individually into one port of a Block Memory Generator block in IP Integrator ... but the Design Rule Checker complains!

 

Paul D

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Teacher muzaffer
Teacher
5,703 Views
Registered: ‎03-31-2012

Re: IP packager BRAM interface

did you try the slave interface? there is a chance the meaning of master/slave is referred to a different frame.
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Adventurer
Adventurer
5,683 Views
Registered: ‎03-05-2008

Re: IP packager BRAM interface

Hi muzaffer,

 

Thanks for your suggestion. Yes, I do get confused about the master/slave port designation ... and I realise that my problem was not entirely the same as the original posting so I've created a new thread.

 

http://forums.xilinx.com/t5/Embedded-Development-Tools/Block-Memory-Generator-in-IPI-memory-size-on-BRAM-PORTA-and-BRAM/m-p/641637

 

and I explain the problem a bit better there.

 

Kind regards

Paul D

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