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Observer trehcir
Observer
5,111 Views
Registered: ‎04-03-2017

IP packager and VHDL-2008

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UG1118 says

says "The IP packager does not support VHDL-2008"

in the "top level hdl requirements."

 

Does this mean that, if I wrap my VHDL-2008 files with an old standard vhdl-file, I'm ok?

 

I'm trying to wrap fixed_pkg_2008.vhd in an ip so that that I can use it through subcore references in several IP.

I wrote a simple top level old standard vhdl file, an encapsulated vhdl-2008 test file, and included the fixed_pkg_2008 file from the vivado/scripts/rt/data directory. This synthesizes in the package manager. However, when I try to package the ip, I get the warnings:

 

[IP_Flow 19-991] Unrecognized or unsupported file 'hdl/fixed_pkg_2008.vhd' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
[IP_Flow 19-991] Unrecognized or unsupported file 'hdl/testFixed.vhd' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
[IP_Flow 19-991] Unrecognized or unsupported file 'hdl/testFixed.vhd' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.Is there something else that I need to fix that the warnings are telling me about? Both my fixed_pkg_2008 file and my encapsulated test file are type "vhdlSource-2008" in the packager.

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Moderator
Moderator
8,559 Views
Registered: ‎11-09-2015

Re: IP packager and VHDL-2008

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Hi @trehcir,

 

In fact @vijayak was right. VHDL-2008 is not supported by the IP packager.

 

I have mixed with systemVerilog. With it you can use a top level wrapper not VHDL-2008. Sorry about that.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Xilinx Employee
Xilinx Employee
5,083 Views
Registered: ‎10-24-2013

Re: IP packager and VHDL-2008

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Hi @trehcir

I don't believe this works,

Thanks,Vijay
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Moderator
Moderator
5,064 Views
Registered: ‎11-09-2015

Re: IP packager and VHDL-2008

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Hi @trehcir,

 

Does this mean that, if I wrap my VHDL-2008 files with an old standard vhdl-file, I'm ok?

EDIT: No it is not supported as per vijay answer

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer trehcir
Observer
5,046 Views
Registered: ‎04-03-2017

Re: IP packager and VHDL-2008

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UG901 says that fixed_pkg_2008.vhd from the vivado/scripts/rt is supported for synthesis. Does that mean there are features supported by vivado that are supported in the IP packager, or am I misunderstanding UG901?

 

Is there a document where can I find out which vhdl-2008 features are not supported in IP packager that are supported elsewhere?

 

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Moderator
Moderator
8,560 Views
Registered: ‎11-09-2015

Re: IP packager and VHDL-2008

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Hi @trehcir,

 

In fact @vijayak was right. VHDL-2008 is not supported by the IP packager.

 

I have mixed with systemVerilog. With it you can use a top level wrapper not VHDL-2008. Sorry about that.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
4,279 Views
Registered: ‎09-20-2017

Re: IP packager and VHDL-2008

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Hi @florentw,

 

can you say us, if there's a support in the near future for vhdl 2008 in ip packager?

Thank you

Franz

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Moderator
Moderator
4,273 Views
Registered: ‎11-09-2015

Re: IP packager and VHDL-2008

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Hi @franzforstmayr,

 

I don't think there is any plan to support it for the moment.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
4,164 Views
Registered: ‎04-22-2008

Re: IP packager and VHDL-2008

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So, wait. The inclusion of a VHDL-2008 file anywhere in the design hierarchy taints everything above it to where the IP Packager can't use it? In 2017? Am I actually understanding that correctly?
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Contributor
Contributor
3,430 Views
Registered: ‎09-20-2017

Re: IP packager and VHDL-2008

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yes exactly.
I had to rewrite lot's of my hdl code for packaging in IP.
I'm not sure, maybe you can add your design as module into your block diagram.
I had to package my project into an IP core, because the gtwizard is not compatible to modules.
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Visitor alefer85
Visitor
2,927 Views
Registered: ‎10-06-2016

Re: IP packager and VHDL-2008

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That's very disappointing.


@florentwwrote:

Hi @franzforstmayr,

 

I don't think there is any plan to support it for the moment.

 

Regards,

 

Florent


 

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Observer cahitugur
Observer
910 Views
Registered: ‎03-31-2014

Re: IP packager and VHDL-2008

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@alefer85 wrote:

That's very disappointing.




Indeed!

I am getting more and more reluctant to work with custom IPs.

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Scholar markcurry
Scholar
894 Views
Registered: ‎09-16-2009

Re: IP packager and VHDL-2008

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Your reluctance is hitting the wrong target.  The proper target of your reluctance should be the Vivado IP packager utility.  Just don't use it.  We never have, and I'm sure we're much more productive because of this choice.

Regards,

Mark

 

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Contributor
Contributor
238 Views
Registered: ‎04-22-2008

Re: IP packager and VHDL-2008

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Hey @markcurry, so you mentioned you don't use IPI (which sounds like a GREAT choice).  What do you do about things that basically require that you do, like processing systems?  Do you build the processor system and all the stock IP into a block diagram, bring a bus interface out of that block, and wire everything from there in HDL?

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Scholar markcurry
Scholar
230 Views
Registered: ‎09-16-2009

Re: IP packager and VHDL-2008

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Processing systems were actually one of the easier things to do.

For PPC405, and PPC440, the EDK was just as awful as the current IPI.  Those being hardcores, were easier to figure out the hard ip boundries, and connect up our RTL there.

For mblaze, we created the most barebones simple version in the dumb tool, then reverse engineered the RTL, and parameters we wished to control from that.  Connected up our peripherals (or even Xilinx ones) to the PLB bus (in the past), AXI bus (today).  We might need to generate a few test versions to make sure we understood all the parameter dependencies.  

Same idea for Zynqs, and MPSoCs - again these are now hard cores again, with a fixed boundary.  Creating sample designs, and reverse engineeering the hard boundary in RTL wasn't too hard.  For MPSOCs, we actually do a little of the opposite - and turn ON all PL connections - such that we get a good example wrapper with all the interfaces.  We can then tie-off interfaces that we're not using as appropriate (hint - use Higher level RTL structures/interfaces/etc to greatly clean this up!)

We do all this without modifying any Xilinx RTL.  We may reverse engineer tool generated wrappers, but we don't modify their IP.

The MPSoCs have a brain dead requirement for the HDF file in order to create the FSBL.  We've not really solved Xilinx' mess here yet.  The boss as tasked me with solving this problem for over a year now, but I haven't got around to it...Sometime dealing with the repeated Xilinx roadblocks they put up (preventing us from using their IP) is just tiresome.

All this reverse engineering that Xilinx likes to push on (all) their customers instead of just making availble simple RTL boundries on the IP.

Regards,

Mark

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