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Newbie
Newbie
7,354 Views
Registered: ‎06-15-2016

IP workflow with external synthesis tool

Hello everyone,

 

I'm asking here because I am experiencing issue with the vivado 2015.2 workflow I am using. I want to use Xilinx IPs with an external synthesis tool (namely synplify pro), but I am experiencing strange issues, so I suppose the steps I am following are not quite right. Here is the workflow I used:

 

  1. Configure the following Xilinx IPs inside a RTL project : Clock wizard, Block rams, AXI EMC, Xilinx MIG. The IPs outputs are generated each into a specific directory that is not the one used for this Vivado project
  2. Use the generated _stub files to trigger black boxes instantiation in the synplify synthesis
  3. Import generated toplevel netlist to another vivado Netlist project, and add the Xilinx IPs to go on with P&R

 

This is I think the quite logical flow (apart the use of a RTL project and not a managed IP project at point 1 if I understand correctly), however the issues start happening on point 3.

I have read I should not directly import DCPs in the Netlist project -because constraints were out of context at the synthesis time- but directly the XCIs. However when I do that, by "import sources -> files -> configures_ip.xci" Vivado fails to recognize the IP as already synthesized, states it does not find the synthesis checkpoint, generates an OOC run for the MIG, and fails to run it (it states it does not find some modules).

 

Were the IPs incorrectly generated? Why does importing a configured IP fails to find DCPs that are right next to the .xci I am importing?

 

Thank you for your answer!

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Moderator
Moderator
7,295 Views
Registered: ‎02-16-2010

AR#63952 provides some known issues with VIVADO 2015.x tool releases. Please check if you are finding one of them matches your observations.
http://www.xilinx.com/support/answers/63952.html

also check ug896, chapter 5
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug896-vivado-ip.pdf
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