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Visitor amer_c
Visitor
5,743 Views
Registered: ‎04-25-2012

IPCoreGen symbol is too large

Hi,

    I use ISE 14.6. When I generate a FIFO symbol using IPCoreGen the resulting symbol is too large and cannot fit in the schematic though it has few pins.

  Any idea ?

Thanks

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2 Replies
Xilinx Employee
Xilinx Employee
5,726 Views
Registered: ‎09-20-2012

Re: IPCoreGen symbol is too large

Hi,

 

Check this article http://www.xilinx.com/support/answers/13615.htm

 

It has the details on how to increase the schematic page size or reduce the symbol size. 

 

Hope it helps,

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor amer_c
Visitor
5,705 Views
Registered: ‎04-25-2012

Re: IPCoreGen symbol is too large

Hello Deepika,

 

    Thanks for your message. I am aware of both suggessions, but that is not an option since increasing page size or reducing symbol size has its shortcomings :

* When updating the modified symbol all changes are lost.

* Printing becomes an issue when the paper size is increased (print too small).

 

 I have worked on several versions of Xilinx beginning from 9.2 and this was not an issue until 14.6. When a generated symbol was relatively larger than expected it could fit however (pre 14.6 versions). Obviously in 14.6 the problem is more evident and annoying.

 

Regards

AC

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