I see this has been asked in several threads, but while it appears a handful of folks have figured it out not enough is posted to the threads for me to understand what exactly I need to do.
The questions is simply how to propagate a frequency value associated with a clock in the block design into a custom IP block. Propagating the clock frequency from a Xilinx IP source into a Xilinx IP target is easy, just hook it up and go. Setting a top-level parameter/generic on a custom IP block with the frequency to use within the block is also easy. However I am failing to understand the incantation necessary to connect the two - evidently it requires a Tcl function but I don't understand where to put it or how to get IP packager to realize the script is present.
I've looked at Xilinx IP sources and see the proc definitions, but I don't understand how they get called. I also don't understand how the value makes it to a VHDL generic or Verilog parameter; the examples I looked at (e.g. uartlite) have a whole lot of other stuff spread across multiple scripts, including calls to tcl libraries that I can't find any definition for.
So could someone who understands how to do it be so kind as to post a complete description of how to propagate a BD-level clock frequency attribute into a VHDL or Verilog custom IP module? Including the minimum tcl scripts needed, where they are supposed to go, and how to get the packager to use them?