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IPI reset net not allowed to be connected to BUFG IP

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Contributor
Posts: 39
Registered: ‎09-12-2007

IPI reset net not allowed to be connected to BUFG IP

I have a high-fanout reset net in my design that I drive with a BUFG. The BUFG is implemented in IPI using the "Utility Buffer" IP core. This method used to work fine in Vivado version 2016.2. I updated Vivado to version 2017.1 and now I am getting a fatal error. The message is below:

CRITICAL WARNING: [BD 41-1170] Cannot connect pins of incompatible types: /proc_sys_reset_dma/peripheral_aresetn(rst) and /buffer_dsp6_rst/BUFG_I(clk)
ERROR: [BD 5-4] Error: running connect_bd_net.
ERROR: [Common 17-39] 'connect_bd_net' failed due to earlier errors.

It looks to me like driving a reset net using a BUFG is no longer possible using the Xilinx Utility Buffer IP core. I can certainly get around this limitation by rolling my own BUFG IP core, but I first wanted to check if there is a way to avoid that.

I know that the pin type of the Utility Buffer input is read-only, so I cannot change that property to be reset type. Is there any other technique I can use to buffer a reset with the Utility Buffer IP?

Thanks!
John

 

Xilinx Employee
Posts: 761
Registered: ‎11-09-2015

Re: IPI reset net not allowed to be connected to BUFG IP

[ Edited ]

Hi @jlevieux,

 

Definition of a BUFG: Primitive: Global Clock Simple Buffer.

 

A reset signal is not a clock signal so why do you want to use a BUFG? Why do you want to use the utility buffer at all? Why not connecting directly the signal?

 

If you connect directly the external port in IPI, an IBUF will be automatically inferred during synthesis.

 

Regards,

 

Florent

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Contributor
Posts: 39
Registered: ‎09-12-2007

Re: IPI reset net not allowed to be connected to BUFG IP

Florent,

 

I need to use the clock buffer BUFG because I have a high fanout reset and that net clogs the routing lanes and makes timing closure much more difficult.

 

In the 7 Series library guide (UG953), the description text for BUFG (page 153 in v2016.2) mentions this usage case:

 

"BUFGs are typically used on clock nets as well other high fanout nets like sets/resets and clock enables."

 

It is important to use the BUFG to drive reset in some cases and I have one such case. I would prefer to use the Xilinx IP core Utility Buffer to do that in IPI rather than roll my own clock/reset buffer. Is there any way that I can do that and avoid the fatal error message "Cannot connect pins of incompatible types"?

 

Note that this BUFG reset design method worked fine in Vivado 2016.2 but is not allowed in 2017.1. Why did this change between the versions?

 

Thanks!

John

 

Xilinx Employee
Posts: 761
Registered: ‎11-09-2015

Re: IPI reset net not allowed to be connected to BUFG IP

Hi @jlevieux,

 

"BUFGs are typically used on clock nets as well other high fanout nets like sets/resets and clock enables."

 

It is important to use the BUFG to drive reset in some cases and I have one such case. I would prefer to use the Xilinx IP core Utility Buffer to do that in IPI rather than roll my own clock/reset buffer.

-> It makes sense

 

So what have changed between 2016.2 and 2017.1, is that the type of the BUFG input for the utility buffer was undef previously and is now clk. I guess the reason for that is because in most of the cases, the BUFG is used for clocks (and the UltraFast methodology guide recommends you to remove the resets as much as possible).

 

As you say, the workaround is to instantiate the BUFG by yourself. This is easy as there is only one input and one input and no configuration or generic value.

For example I have done it in the attached VHDL file (only copying the template from UG181). To add it in IPI in 2017.1:

-> First, add the file to vivado

-> In the sources window, right click on the file and click "Add module to Block Design" (<- easy way to add to IPI)

-> Then you just have to connect it

 

Hope that helps,

 

Regards,

 

Florent

--------------------------------------------------------------------------------------------
Please mark an answer "Accept as solution" if a post has the solution to your issue.

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Contributor
Posts: 39
Registered: ‎09-12-2007

Re: IPI reset net not allowed to be connected to BUFG IP

Hi Florent,

 

I figured out a workaround to connecting the reset net to a BUFG in my IPI design and still use the Xilinx "Utility Buffer" IP core. I created a "pass-through" block that converts the reset net into an ordinary net that can be connected directly to the input of the "Utility Buffer" (BUFG) in IPI and avoids both (a) the DRC fatal error about connecting a reset pin to a clock pin and (b) rolling my own BUFG IP core in order to accept reset input signal types.

 

To make the "pass-through" block, I used the "util_reduced_logic" block configured with only a single input which passes the input through to the output unaltered. Using this technique, the design built to a BIT file and passed all hardware diagnostic tests.

 

I would like to request that Xilinx please consider making a future change to the "Processor System Reset" IP core to make it configurable to drive the reset output pin(s) with a BUFG as an option?

 

Thanks!
John