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IPI reset net not allowed to be connected to BUFG IP

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Participant
Posts: 35
Registered: ‎09-12-2007

IPI reset net not allowed to be connected to BUFG IP

I have a high-fanout reset net in my design that I drive with a BUFG. The BUFG is implemented in IPI using the "Utility Buffer" IP core. This method used to work fine in Vivado version 2016.2. I updated Vivado to version 2017.1 and now I am getting a fatal error. The message is below:

CRITICAL WARNING: [BD 41-1170] Cannot connect pins of incompatible types: /proc_sys_reset_dma/peripheral_aresetn(rst) and /buffer_dsp6_rst/BUFG_I(clk)
ERROR: [BD 5-4] Error: running connect_bd_net.
ERROR: [Common 17-39] 'connect_bd_net' failed due to earlier errors.

It looks to me like driving a reset net using a BUFG is no longer possible using the Xilinx Utility Buffer IP core. I can certainly get around this limitation by rolling my own BUFG IP core, but I first wanted to check if there is a way to avoid that.

I know that the pin type of the Utility Buffer input is read-only, so I cannot change that property to be reset type. Is there any other technique I can use to buffer a reset with the Utility Buffer IP?

Thanks!
John

 

Xilinx Employee
Posts: 638
Registered: ‎11-09-2015

Re: IPI reset net not allowed to be connected to BUFG IP

[ Edited ]

Hi @jlevieux,

 

Definition of a BUFG: Primitive: Global Clock Simple Buffer.

 

A reset signal is not a clock signal so why do you want to use a BUFG? Why do you want to use the utility buffer at all? Why not connecting directly the signal?

 

If you connect directly the external port in IPI, an IBUF will be automatically inferred during synthesis.

 

Regards,

 

Florent

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Participant
Posts: 35
Registered: ‎09-12-2007

Re: IPI reset net not allowed to be connected to BUFG IP

Florent,

 

I need to use the clock buffer BUFG because I have a high fanout reset and that net clogs the routing lanes and makes timing closure much more difficult.

 

In the 7 Series library guide (UG953), the description text for BUFG (page 153 in v2016.2) mentions this usage case:

 

"BUFGs are typically used on clock nets as well other high fanout nets like sets/resets and clock enables."

 

It is important to use the BUFG to drive reset in some cases and I have one such case. I would prefer to use the Xilinx IP core Utility Buffer to do that in IPI rather than roll my own clock/reset buffer. Is there any way that I can do that and avoid the fatal error message "Cannot connect pins of incompatible types"?

 

Note that this BUFG reset design method worked fine in Vivado 2016.2 but is not allowed in 2017.1. Why did this change between the versions?

 

Thanks!

John