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Visitor
Visitor
5,063 Views
Registered: ‎12-23-2008

ISE 13.1 coregen. MIG 3.7 (Virtex6). RDIMM DualRank - error on MAP.

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I created MIG core version 3.7 for Virtex6 (xc6vlx130t, ff1156, speed grade 2).

You can see project file in attachment.

 

During map I got an error:
 

************************************

LIT:667 - Block 'MMCM_ADV symbol   "physical_group_U_Ram_Ctrl/u_infrastructure/clk_pll/U_Ram_Ctrl/u_infrastructure/u_mmcm_adv"' has its target frequency, FVCO, out of range. Valid FVCO   range for speed grade "-2" is 600MHz - 1200MHz. The computed FCVO is a  function of the input frequency CLKIN1_PERIOD, the division factor   DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F attribute (FVCO =   1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). The CLKIN_PERIOD   attribute may have been set by ngdbuild based on the user specified PERIOD   constraint. The current calculated FVCO is 1212.121212 MHz. Reference the V6   architecture Users Guide or search the Xilinx Answer Records database for the  error code.

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If I override clock period from 3.3 ns to 3.334 ns I don't get an error.

Nevertheless the only valid clock period for this block is 3.3 ns. The questions:

1. Is this workaround correct?
2. Can i get any further problem (the real clock period will be 3.3 ns)?
3. Is this problem of CoreGenerator?

4. Is there any "official" workaround?

 

Thank you.

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Xilinx Employee
Xilinx Employee
6,341 Views
Registered: ‎10-23-2007

The VCO max frequency for the -2 is 1440 MHz (see DS152).  In your case it almost seems like you are seeing the -1 limit of 1200 MHz.

 

I created a fresh design using MIG 3.8 in 13.2 at 3.3 ns with the same dual rank DIMM and it ran through the tools without any problem.

 

I suppose this could have changed between 13.1 and 13.2, but is there any chance you've somehow told the tools that you have a -1 and not a -2?

 

[ by the way, there is a MIG forum that would be a better place for these questions ]

 

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Xilinx Employee
Xilinx Employee
6,342 Views
Registered: ‎10-23-2007

The VCO max frequency for the -2 is 1440 MHz (see DS152).  In your case it almost seems like you are seeing the -1 limit of 1200 MHz.

 

I created a fresh design using MIG 3.8 in 13.2 at 3.3 ns with the same dual rank DIMM and it ran through the tools without any problem.

 

I suppose this could have changed between 13.1 and 13.2, but is there any chance you've somehow told the tools that you have a -1 and not a -2?

 

[ by the way, there is a MIG forum that would be a better place for these questions ]

 

View solution in original post

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Visitor
Visitor
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Registered: ‎12-23-2008

The problem was in wrong device. xc6vcx instead of xc6vlx.

 

Thanks.

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