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Explorer
Explorer
8,144 Views
Registered: ‎09-23-2011

ISE 13.4 ERROR:coreutil:1010

Hi , I've recently migrated to 13.4 from 12.4 and I'm using fedora 15.When I try to generate MAC core i get  error:coreutil:1010 error with 

1)returning a non-zero exit code '2' 

2)./../netgen: application received signal 11.

3)error:sim Error found during generation.

4)error:sim - Failed to generate 'MAC' . An error encountered during generation.Please see the log for details.

5)Error:sim:877 - Error found during execution of IP 'Ten Gigabit Ethernet MAC v10.'

 

Have you faced any similar issues ? 

 

Thank you

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-22-2008

Is this the only error that you see. 

I searched through our case logs and found three cases with this error but all were preceeded by another error first. 

I also did a google search and found several hits (many from Xilinx users).  Most of the hits suggested a relation a kernal upgrade.

If you want to get a more complete coregen log run coregen with debug mode and java verbose messaging turned on (coregen -ddd -J verbose).

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Visitor
Visitor
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Registered: ‎05-04-2010


@howardp wrote:

Is this the only error that you see. 

I searched through our case logs and found three cases with this error but all were preceeded by another error first. 

I also did a google search and found several hits (many from Xilinx users).  Most of the hits suggested a relation a kernal upgrade.

If you want to get a more complete coregen log run coregen with debug mode and java verbose messaging turned on (coregen -ddd -J verbose).


I have the same problem. It seems related to netgen on Fedora 15 (14 is fine). The good.ngc contains the 10G MAC netlist generated on another machine. I tried both 13.2 and 13.3 and they behaves the same. I haven't tried 13.4 though.

 

My machine

[XXX@XXX small]$ uname -a
Linux XXX 2.6.42.3-2.fc15.x86_64 #1 SMP Thu Feb 9 01:42:06 UTC 2012 x86_64 x86_64 x86_64 GNU/Linux

 

[XXX@XXX small]$ netgen -w -ofmt verilog good.ngc
Release 13.3 - netgen O.76xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.

Command Line: netgen -w -ofmt verilog good.ngc

Reading design 'good.ngc' ...
Flattening design ...
Processing design ...
Preping design's networks ...
Preping design's macros ...
Writing Verilog netlist file 'good.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
simulation primitives and has to be used with UNISIM simulation library for
correct compilation and simulation.
Number of warnings: 0
Number of info messages: 1
Total memory usage is 328080 kilobytes

Created netgen log file 'good.nlf'.
Segmentation fault (core dumped)

 

When doing a dmesg

[XXX@XXX small]$ dmesg | tail -n 4
[ 4957.178926] netgen[2848]: segfault at 0 ip 00007f030ae7a80f sp 00007fff7322fa00 error 4 in libxalanc.so[7f030ab8d000+40e000]
[ 5782.916444] netgen[2927]: segfault at 18 ip 00007f08edd04812 sp 00007fff948d21b0 error 4 in libxalanc.so[7f08eda17000+40e000]
[ 5825.965135] netgen[2935]: segfault at 18 ip 00007fc3b0453812 sp 00007fff5d07dbe0 error 4 in libxalanc.so[7fc3b0166000+40e000]
[ 6051.180474] netgen[2950]: segfault at 0 ip 00007f42e0ca780f sp 00007fffd3af53d0 error 4 in libxalanc.so[7f42e09ba000+40e000]

 

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Visitor
Visitor
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Registered: ‎05-04-2010


@eastzone wrote:

@howardp wrote:

Is this the only error that you see. 

I searched through our case logs and found three cases with this error but all were preceeded by another error first. 

I also did a google search and found several hits (many from Xilinx users).  Most of the hits suggested a relation a kernal upgrade.

If you want to get a more complete coregen log run coregen with debug mode and java verbose messaging turned on (coregen -ddd -J verbose).


I have the same problem. It seems related to netgen on Fedora 15 (14 is fine). The good.ngc contains the 10G MAC netlist generated on another machine. I tried both 13.2 and 13.3 and they behaves the same. I haven't tried 13.4 though.

 

My machine

[XXX@XXX small]$ uname -a
Linux XXX 2.6.42.3-2.fc15.x86_64 #1 SMP Thu Feb 9 01:42:06 UTC 2012 x86_64 x86_64 x86_64 GNU/Linux

 

[XXX@XXX small]$ netgen -w -ofmt verilog good.ngc
Release 13.3 - netgen O.76xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.

Command Line: netgen -w -ofmt verilog good.ngc

Reading design 'good.ngc' ...
Flattening design ...
Processing design ...
Preping design's networks ...
Preping design's macros ...
Writing Verilog netlist file 'good.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
simulation primitives and has to be used with UNISIM simulation library for
correct compilation and simulation.
Number of warnings: 0
Number of info messages: 1
Total memory usage is 328080 kilobytes

Created netgen log file 'good.nlf'.
Segmentation fault (core dumped)

 

When doing a dmesg

[XXX@XXX small]$ dmesg | tail -n 4
[ 4957.178926] netgen[2848]: segfault at 0 ip 00007f030ae7a80f sp 00007fff7322fa00 error 4 in libxalanc.so[7f030ab8d000+40e000]
[ 5782.916444] netgen[2927]: segfault at 18 ip 00007f08edd04812 sp 00007fff948d21b0 error 4 in libxalanc.so[7f08eda17000+40e000]
[ 5825.965135] netgen[2935]: segfault at 18 ip 00007fc3b0453812 sp 00007fff5d07dbe0 error 4 in libxalanc.so[7fc3b0166000+40e000]
[ 6051.180474] netgen[2950]: segfault at 0 ip 00007f42e0ca780f sp 00007fffd3af53d0 error 4 in libxalanc.so[7f42e09ba000+40e000]

 


Update:

 

This problem seems related to 

 

http://www.xilinx.com/support/answers/43865.htm

http://forums.xilinx.com/t5/EDK-and-Platform-Studio/Core-dump/td-p/144456

 

When adding LD_PRELOAD=/tools/xilinx/13.1/ISE_DS/ISE/lib/lin64/libXst2_Core.so to netgen, it stops crashing. However, it doesn't work when add that with coregen since netgen is a subprocess. When doing a "dmesg" I can still see the same netgen crashes.

 

Fedora 15 uses glibc 2.14, while Fedora 14 uses glibc 2.13. So this can be the source of difference.

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Newbie
Newbie
7,866 Views
Registered: ‎08-29-2012

Hello,

 

I've been having the same problem in my Ubuntu.

All I've tried to is to add an Tri-Mode Ethernet MAC Core source to my (empty) project.

It returns:

 

Generating VHDL structural model.
ERROR:coreutil:1010 - Command '/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/netgen
   -intstyle ise -w -sim -ofmt vhdl "./tmp/_cg/ethx.ngc" "./tmp/_cg/ethx.vhd"'
   failed, returning a non-zero exit code '2':
   /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/netgen: application received signal 6.
ERROR:sim - Error found during generation.
ERROR:sim - Failed to generate 'ethx'.  An error encountered during generation.
   Please see the log for details.
Wrote CGP file for project 'ethx'.

I've searched for a glibc package in my system, but I haven't found one.

Then I've tried to apt-get install glibc and haven't found a package in the Ubuntu repo.

Should I download the package from GNU C page (I'd rather not)?

Did installing the previous version of this library solve the problem for you?

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