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Registered: ‎08-31-2009

ISE: Creating a custom AXI4 component

I have an ISE project with a number of VHDL modules that I would like to refactor and convert to AXI4 interfaces. This is analogous to the Vivado "Create a new AXI4 peripheral". What is the workflow for doing this in ISE?


It seems like this would just be in the language templates, where there would be a wrapper containing the interface signals and some decoding logic. Vivado provides exactly this when creating an AXI4 peripheral. I don't find it in ISE.


I see some references for doing this using EDK, but I am not building a processor based system, and don't have EDK.


I also see references to AR# 37425, which has template files, but they only define the signals and do not provide code for interacting with the bus.


Or perhaps there is non-Xilinx documentation out there which provides examples of builiding AXI4 based systems from scratch?





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Teacher muzaffer
Registered: ‎03-31-2012

Re: ISE: Creating a custom AXI4 component

@charlesmartin The code generated by Vivado is pretty generic RTL which you can use in ISE. I'd just generate on template AXI slave (lite or full depending on your needs) and add your custom code to it to use with ISE.

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