06-01-2017 02:29 PM
VHDL support in Vivado is documented in the "Synthesis User Guide" (UG901) chapter 6.
VHDL support for ISE is documented in the "XST User Guide for Virtex-6, Spartan-6, and 7 series Devices", UG687, chapter 3.
06-01-2017 05:24 PM
@sprl111 "... document that succinctly summarizes that portions of the VHDL language is supported in ISE? Ditto for VIVADO?"
Chapter 14 XST VHDL Language Support
This is the best of the Xilinx synthesis reference manuals for VHDL in terms of organization-for-usability, and accuracy in describing language support for the synthesizer version at hand.
Chapter 3 VHDL Support
This version is less organized, and suffers from a lack of updating in its' later years to track the language improvements made to XST.
Chapter 5: VHDL Support
This chapter is a trainwreck, consisting of a badly reformatted XST manual chapter whose content was never properly updated to reflect actual Vivado Synthesis language support.
Chapter 6: VHDL-2008 Language Support
This chapter was written for Vivado, and as such is better in accuracy (although some of the 'supported' constructs don't actually synthesize correctly); but it is missing much VHDL-2008 information (e.g. package generics, contexts, etc)
Vivado's support for VHDL is poor- code that has synthesized for decades in other tools will fail, often silently, generating bad logic. 'Advanced' synthesizable VHDL (functions, procedures, records, memory initialization file readers,etc. ) is hit-or-miss, it's best to perform post-synthesis simulations to see whether Vivado synthesis actually worked.
When moving large bodies of old ISE code to Vivado, even simple things like synthesis attributes have been changed, so one generally has to touch much of the code to make it work, thanks to Vivado's who-needs-backwards-compatibility philosophy.
Many Vivado IP cores are now delivered as Verilog-only RTL.
Simulation in Vivado no longer supports the VHDL SIMPRIM library, so any timing simulations need to be done in Verilog.
IP Integrator support for packaging VHDL is crippled to plain-old-Verilog-equivalent port/generic types, and doesn't support VHDL-2008.
I could go on for pages, but essentially Xilinx seems to have lost all institutional knowledge of VHDL when architecting and implementing Vivado.