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Visitor
Visitor
5,184 Views
Registered: ‎07-29-2016

Idle Signals to Produce with External full AXI slave

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Hi,

 

I'm trying to create a design where I have an external full AXI slave (with the ZYNQ processor as the master), but for the moment I just want to create the connection and run my design like normal as if the slave were idle. The problem I'm having is that when I try to run my software, it crashes during start up (only change between working version and failing version is the introduction of this external slave). My question is does anybody know the proper signals I'm supposed to be feeding the ZYNQ master so that it will see my slave as idle and continue on?

 

Thank you for any help.

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Teacher
Teacher
9,681 Views
Registered: ‎03-31-2012
If I understand your question properly, what you need is to set all x_ready signals of master driven channels (like aw_ready) to 0 and set all x_valid signals of slave driven channels (ie bvalid) to 0.
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Teacher
Teacher
9,682 Views
Registered: ‎03-31-2012
If I understand your question properly, what you need is to set all x_ready signals of master driven channels (like aw_ready) to 0 and set all x_valid signals of slave driven channels (ie bvalid) to 0.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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Visitor
Visitor
5,062 Views
Registered: ‎07-29-2016

That did it!

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