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## Illegal redeclaration???

Visitor
Posts: 18
Registered: ‎06-20-2011

# Illegal redeclaration???

This is my codes

`timescale 1ns / 1ps

`define Digit 20

`define PACK_ARRAY(PK_WIDTH,PK_LEN,In,Out)  genvar pk_idx; generate for(pk_idx=0; pk_idx<(PK_LEN); pk_idx=pk_idx+1) begin:PACK assign Out[pk_idx][((PK_WIDTH)-1):0]=In[((PK_WIDTH)*pk_idx+((PK_WIDTH)-1)):((PK_WIDTH)*pk_idx)]; end endgenerate﻿

module Prefix_carrytree(Ain,Gin,Cin,Cout,C    );

input  [79:0] Ain  ;

input  [79:0] Gin;

input Cin;

output reg Cout;

output reg [79:0]C;

wire [3:0] A[20:0];

wire [3:0] G[20:0];

`PACK_ARRAY(4,20,Ain,A)

`PACK_ARRAY(4,20,Gin,G)﻿

To make it simple, I am try to pack a vector [79:0] into an array of 4*20.

However, when I call the second PACK_ARRAY, it says the pk_idx is illegal redeclaraed. Can anyone help me about it???

Scholar
Posts: 8,385
Registered: ‎08-14-2007

## Re: Illegal redeclaration???

A genvar is local to a generate loop and can be re-used.  However the proper syntax places the

genvar declaration inside the loop like:

`define PACK_ARRAY(PK_WIDTH,PK_LEN,In,Out) \

generate \

genvar pk_idx; \

for(pk_idx=0; pk_idx<(PK_LEN); pk_idx=pk_idx+1) ﻿\

begin:PACK assign \

Out[pk_idx][((PK_WIDTH)-1):0]=In[((PK_WIDTH)*pk_idx+((PK_WIDTH)-1)):((PK_WIDTH)*pk_idx)]; \

end \

endgenerate﻿

You can also use several lines to make your macro definition more readable as shown above.

From the Verilog LRM:

"The macro text can be any arbitrary text specified on the same line as the text macro name. If more than one
line is necessary to specify the text, the newline shall be preceded by a backslash (\). The first newline not
preceded by a backslash shall end the macro text. The newline preceded by a backslash shall be replaced in
the expanded macro with a newline (but without the preceding backslash character).﻿"

﻿

-- Gabor
Visitor
Posts: 18
Registered: ‎06-20-2011

## Re: Illegal redeclaration???

I tried your method and it's still not working.

`timescale 1ns / 1ps`define Digit 20

`define PACK_ARRAY(PK_WIDTH,PK_LEN,In,Out) \

generate\

genvar pk_idx;\

for(pk_idx=0; pk_idx<(PK_LEN); pk_idx=pk_idx+1) begin:PACK\

assign Out[pk_idx][((PK_WIDTH)-1):0]=In[((PK_WIDTH)*pk_idx+((PK_WIDTH)-1)):((PK_WIDTH)*pk_idx)];\

end \

endgenerate﻿

And the error is

line 5 expecting 'EOF', found 'genvar'﻿

Scholar
Posts: 8,385
Registered: ‎08-14-2007

## Re: Illegal redeclaration???

The compiler seems to be having a problem with the line extensions, hence the error is on

line 5 in the middle of the `define and not lower down where the macro is called.

Check to make sure there are no trailing spaces after the backslash at the end of each line

in the macro definition.  The "\" character needs to be the last character in the line.  Otherwise

the character after the backslash (space or tab) is treated as the escaped character rather

than the newline.  It's O.K. to have spaces between the end of the text in the line and the

backslash character.

i.e. - using underscores to represent spaces:

generate___\

is O.K.

generate_\_

is not O.K.

-- Gabor

-- Gabor
Visitor
Posts: 18
Registered: ‎06-20-2011

## Re: Illegal redeclaration???

The redeclaration error is still there. It seems once a 'genvar' is defined, we cannot define it again in another generate. I wonder if there is a way to release the genvar variable after one generate is over?

Scholar
Posts: 8,385
Registered: ‎08-14-2007

## Re: Illegal redeclaration???

I would have thought that this is a bug, given that the genvar scope should be local to each generate loop.

A workaround would be to take the genvar definition out of the macro and place it once before the macro

is called like:

wire [3:0] A[20:0];

wire [3:0] G[20:0];

genvar pk_idx;﻿

`PACK_ARRAY(4,20,Ain,A)

`PACK_ARRAY(4,20,Gin,G)﻿

﻿

Two generate loops may use the same genvar as long as the loops are not nested.

HTH,

Gabor

-- Gabor
Participant
Posts: 39
Registered: ‎03-03-2008

## Re: Illegal redeclaration???

Good one Gabor. For what it's worth, the code compiles for me.

David

"You don't scare me, Bob."