I am new to VHDL, I would like to implement Arrays Initialization, declaration in VHDL, I need to assign 8 individual input signals to an array1(array of 8 elements), assign that initialized array to array2(array of 8 elements), and extract 8 individual signals from array 2 and assign them to 8 individual output signals.
Any suggestions, examples, steps to implement regarding this would be greatly appreciated.
I assume your input and output signals are std_logic_vector. Why do you want to use arrays in this example? Because your inputs and outputs are individual signals, you would have to assign to/from them manually
type slv_a is array(natural range<>) of std_logic_vector(2 downto 0);
signal array1, array2 : slv_a(7 downto 0);
-- assign array1 from inputs:
array1(0) <= IN_SIGNAL0;
array1(1) <= IN_SIGNAL1;
-- assign outputs from array2:
OUT_SIGNAL0 <= array2(0);
OUT_SIGNAL1 <= array2(1);
-- array2 is array1:
array2 <= array1;
What do you mean when you ask about initialisation? Is the above code snippet answering your questions?