UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer olagrottvik
Observer
995 Views
Registered: ‎12-04-2017

Inconsistent port type when using Block Design

Hi,

 

I'm using Block Design to manage a large AXI Interconnect tree. Most of the AXI slaves are connected in RTL code via the Block design wrapper code generated by Vivado. However, when making multiple AXI connections external, there seem to be inconsistencies whether single-bit signals should be created as std_logic_vector(0 downto 0) or just a simple std_logic.

 

Skjermbilde.PNG

Skjermbilde2.PNG

The same bus type, AXI4LITE, but different signal types...

Skjermbilde3.PNG

 

Also, whenever I update the Block Design with something, there seems to be a chance that these signals may change to the other type. This is very annoying since I then have to change my instantiation code as well.

 

Is there some way to make Vivado choose a signal type?

Tags (1)
9 Replies
Moderator
Moderator
932 Views
Registered: ‎09-15-2016

Re: Inconsistent port type when using Block Design

Hi @olagrottvik,

 

Does this post help?

https://forums.xilinx.com/t5/Welcome-Join/Getting-std-logic-vector-0-to-0-instead-of-std-logic-in-vivado/td-p/657959

 

Thanks

Prathik

-----------------------------------------------------------------------------------

Don't forget to reply, kudo, and mark the appropriate post as 'accept as solution'.

-----------------------------------------------------------------------------------

 

0 Kudos
Observer olagrottvik
Observer
900 Views
Registered: ‎12-04-2017

Re: Inconsistent port type when using Block Design

Hi,

 

Thanks for your reply, but my question is not how to connect a std_logic to a std_logic_vector(0 downto 0).

 

The problem is that Vivado is not consistent, and whenever I make a change in the block design I need to update several hundred lines of code. Why would Vivado, or the AXI Interconnect have the option to randomize which signal it uses...

 

After some experiments, it looks like that if I connect an XBAR after the AXI interconnect, the signals are consistent (all stay std_logic_vector(0 downto 0). This is extremely annoying as well, and not an acceptable workaround if you ask me.

0 Kudos
Contributor
Contributor
637 Views
Registered: ‎06-25-2012

Re: Inconsistent port type when using Block Design

Did you ever find another solution to this issue?

It has been very frustrating to me as well. It seems like Vivado randomly decides if AXI ports leaving the block diagram have signals (like arready, arvalid, etc) are a std_logic_vector of 0 downto 0 or simply std_logic.

I have had this issue for Vivado versions ranging from 2015.x - 2017.4.

 

I can make small changes to my block design and it "randomly" swaps back and forth breaking the top level that I place my block design in.  Even two AXI-MM ports connected to the same AXI Interconnect can have different representations.

 

0 Kudos
Observer olagrottvik
Observer
631 Views
Registered: ‎12-04-2017

Re: Inconsistent port type when using Block Design

Sadly, I have not, and it does not seem like Xilinx care about this, even though it is extremely time-consuming to fix for changes. Maybe the type of workflow where you export the signals out of block diagram is unprioritized.

I'm using 2018.2 now, and I still see this behavior. I've unsuccessfully tried to modify things and look for patterns for a choice of signal type.

0 Kudos
Contributor
Contributor
629 Views
Registered: ‎06-25-2012

Re: Inconsistent port type when using Block Design

Have you tried to make a support ticket?

From my past support experience I am guessing that it could take quite some effort to arrive at point of mutual understanding and replicating the problem.

0 Kudos
Contributor
Contributor
533 Views
Registered: ‎06-25-2012

Re: Inconsistent port type when using Block Design

I created a support request.

Support indicated: This looks to be a bug as scalar ports should always be std_logic type. I am not sure why the tool is giving inconsistent result and changing it to wrong type “std_logic_vector (0 down to 0)”

Support suggested a wrapper could be made in verilog instead, or the wrapper could be manually maintained.

I will update if bug gets confirmed and CR gets filed.

0 Kudos
Observer olagrottvik
Observer
531 Views
Registered: ‎12-04-2017

Re: Inconsistent port type when using Block Design

Thanks for the update!

I have not had the time to post support yet, so thanks for the help with that!

0 Kudos
Contributor
Contributor
493 Views
Registered: ‎06-25-2012

Re: Inconsistent port type when using Block Design

The bug was confirmed by Xilinx and CR-1020027 was opened.

Additionally Xilinx confirmed that this issue was still present in the internal build of 2019.1.

0 Kudos
Contributor
Contributor
223 Views
Registered: ‎06-25-2012

Re: Inconsistent port type when using Block Design

I recently got an update from Xilinx.

They indicated the Change Request (CR-1020027) is now "Closed (Never Fix)"

 

0 Kudos