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Participant jesperjustesen
Participant
1,823 Views
Registered: ‎01-19-2016

Infer IP's used in design before calling read_ip

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Hi

I am using non-project mode.
I have various defines that will enable/disable the use of IP's within my design.

Until now I have just been include all IP's, whether or not they where actually used in the design.
Unfortunately this will cause this critical warning "[Designutils 20-1280] Could not find module 'fifo...." whenever I synthesize (synth_design). The warning will be present for each IP that are not used.

I have done some investigation in how "unused" IP's are handled in an ordinary Vivado GUI project.
If I have a pristine Vivado project in which a list of IP's is listed it could look like this.


raw.PNG

Then, as soon as I open the project the very first time, an "AutoDisabled" property is applied to IP's that are not used in the project.

 

after_open.PNG

I would like to do something similar in non-project mode. In this way I would avoid adding IP's that are not used and i would get rid of the critical warning.

Rough suggestion for what I want to do:

read_verilog {some_file.v other_file.v}
set used_ips ["get_used_ips"]
read_ip $used_ips
synth_design; # NOW RUNNING WITHOUT ANY WARNINGS ABOUT ANY UNUSED IP'S

Any suggestions on how to "get_used_ips"?

 

Best regards

Jesper

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Participant jesperjustesen
Participant
2,299 Views
Registered: ‎01-19-2016

Re: Infer IP's used in design before calling read_ip

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Hi

 

Thank you for your commitment to help me!

 

I am actually able to use "remove_files" in between elaboration and synthesis, so i will go for solution number 3. below.

 

1. Clean project between elaboration and synthesis

read_verilog    $filesV
read_ip         $filesIP
synth_design -rtl           # Elaborate design
filesIPfiltered [used_ips]
clean_project   
read_verilog    $filesV
read_ip         $filesIPfiltered
synth_design                # Synthesize design

 

2. Temporarily use IP stub files to treat them as blackboxes

read_verilog    $filesV
read_verilog    [find_IP_stubs]
synth_design -rtl           # Elaborate design
filesIPfiltered [used_ips]
read_ip         $filesIPfiltered
synth_design                # Synthesize design

 

3. Use "remove_files" to remove unused IP's between elaboration and synthesis

read_verilog    $filesV 
read_ip $filesIP synth_design -rtl # Elaborate design filesIPNotUsed [not_used_ips] remove_files $filesIPNotUsed synth_design # Synthesize design

 

Comments about the different solutions:

1. Clean_project seems a bit drastic to use.

2. I feel that the code needed to find the stubs would add unnecessary complexity ("unpack" core containers, find stubs, etc.)     (Okay, maybe not that complex, but anyway)

3. Simple and readable.

 

By the way; The second time i call synth_design for the full synthesis i am pretty sure that i am not able to skip "elaboration" although i have done elaboration once!? I conclude this after trying and also based on this post https://forums.xilinx.com/t5/Vivado-TCL-Community/Vivado-XDC-and-TCL/td-p/281668/page/2

 

Best regards

Jesper

 

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9 Replies
Xilinx Employee
Xilinx Employee
1,788 Views
Registered: ‎09-20-2012

Re: Infer IP's used in design before calling read_ip

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Hi @jesperjustesen

 

You can elaborate the design and search for cells which are black boxes. You can then get the reference name of those black box cells and look for matching IP's in the design. If it matches to any of the IP name, you can include that in the used_ips list.

 

synth_design -rtl //elaborates design

get_cells -hierarchical -filter { IS_BLACKBOX == "TRUE" } //returns all black box cells

get_property REF_NAME [get_cells -hierarchical -filter { IS_BLACKBOX == "TRUE" }] //returns the reference name. 

 

Compare the reference name returned by above command with list of IP files. If there is a match, then store that IP name is used_ips vairable.

 

Hope this helps.

Thanks,
Deepika.
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Participant jesperjustesen
Participant
1,769 Views
Registered: ‎01-19-2016

Re: Infer IP's used in design before calling read_ip

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Hi Deepika

Thank you for your answer. It seems very useful!

I tried filtering on IS_BLACKBOX but did not have any great success. It seems somehow that none of the cells has it's IS_BLACKBOX property set. I tried inspecting the properties in a Vivado GUI project and here as well I was not able to find any cell with IS_BLACKBOX set.

 

cell.PNG

Instead I have done something similar. I search for cells where the IP name either matches REF_NAME or ORIG_REF_NAME. In the simple case below I just search for a hard-coded IP name, but eventually I would of course loop and search based on the list of IP's.

[get_cells -hierarchical -filter {REF_NAME == fifo_8_4096_br_pef_ic    ||  ORIG_REF_NAME == fifo_8_4096_br_pef_ic}]

Do you think this is a viable way of doing it?

By the way I am wondering about the most correct way to do the elaboration and then the subsequent synth.
It seems necessary to use close_project before once more reading in the IP's (which now only includes IP's that are actually used).
    

read_verilog    $filesV
read_ip         $filesIP

synth_design -rtl           # Elaborate design

filesIPfiltered [used_ips]

close_project               # ????? 

read_verilog    $filesV
read_ip         $filesIPfiltered

synth_design                # Synthesize design

 

Best regards

Jesper

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Xilinx Employee
Xilinx Employee
1,761 Views
Registered: ‎09-20-2012

Re: Infer IP's used in design before calling read_ip

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Hi @jesperjustesen

 

You need not use close_project command. The second synth_design command will elaborate the design again.

 

If you just read the top level RTL and elaborate the design, the IP's will be black boxes. You can then search for these blackboxes to find the IP's which are instantiated in the design.

Thanks,
Deepika.
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Participant jesperjustesen
Participant
1,757 Views
Registered: ‎01-19-2016

Re: Infer IP's used in design before calling read_ip

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Hi

 

I am sorry but i don't completely get it.

 

What you saying is that calling read_ip the second time (now with a filtered list) will "clear" the old list of read IP's?

And that makes close_project unnecessary?

 

read_verilog    $filesV
read_ip         $filesIP

synth_design -rtl           # Elaborate design

filesIPfiltered [used_ips]

read_ip         $filesIPfiltered

synth_design                # Synthesize design

Thanks

Jesper

 

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Xilinx Employee
Xilinx Employee
1,755 Views
Registered: ‎09-20-2012

Re: Infer IP's used in design before calling read_ip

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Hi @jesperjustesen

 

Remove the first read_ip command. Just read the RTL and the elaborate. In the elaborated design look for the IP instances which are Black boxes. Then read in those used IP's. After this run synth_design. 

 

read_verilog    $filesV

synth_design -rtl           # Elaborate design

filesIPfiltered [used_ips]

read_ip         $filesIPfiltered

synth_design                # Synthesize design

 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Participant jesperjustesen
Participant
1,751 Views
Registered: ‎01-19-2016

Re: Infer IP's used in design before calling read_ip

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Hi

 

I guess the reason for my confusion is that i am not able to elaborate design without reading the IP's first.

If i do not read IP's (read_ip) before elaboration (synth_design -rtl) i will get an error "[Synth 8-439] module 'fifo_8_256_dr_cc' not found" as soon as the first IP is needed.

 

I suspect that this is happening because i haven't been able to state that the IP's is black boxes?

 

I am maintaining the IP's in a separate project and what i provide to the "main project" is a list of xcix files ($filesIP).

 

Best regards

Jesper

 

 

 

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Xilinx Employee
Xilinx Employee
1,694 Views
Registered: ‎09-20-2012

Re: Infer IP's used in design before calling read_ip

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Hi @jesperjustesen

 

I dont think there is a command to flush out the files read in to memory.

 

To avoid this error during elaboration you have to read the IP stub file (_stub.v/vhd) located at .srcs\sources_1\ip\ip_name. Below script should work.

 

read_verilog    $filesV
read_verilog    $IPstubfiles

synth_design -rtl           # Elaborate design

filesIPfiltered [used_ips]

read_ip         $filesIPfiltered

synth_design                # Synthesize design

 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Highlighted
Participant jesperjustesen
Participant
2,300 Views
Registered: ‎01-19-2016

Re: Infer IP's used in design before calling read_ip

Jump to solution

 

 

Hi

 

Thank you for your commitment to help me!

 

I am actually able to use "remove_files" in between elaboration and synthesis, so i will go for solution number 3. below.

 

1. Clean project between elaboration and synthesis

read_verilog    $filesV
read_ip         $filesIP
synth_design -rtl           # Elaborate design
filesIPfiltered [used_ips]
clean_project   
read_verilog    $filesV
read_ip         $filesIPfiltered
synth_design                # Synthesize design

 

2. Temporarily use IP stub files to treat them as blackboxes

read_verilog    $filesV
read_verilog    [find_IP_stubs]
synth_design -rtl           # Elaborate design
filesIPfiltered [used_ips]
read_ip         $filesIPfiltered
synth_design                # Synthesize design

 

3. Use "remove_files" to remove unused IP's between elaboration and synthesis

read_verilog    $filesV 
read_ip $filesIP synth_design -rtl # Elaborate design filesIPNotUsed [not_used_ips] remove_files $filesIPNotUsed synth_design # Synthesize design

 

Comments about the different solutions:

1. Clean_project seems a bit drastic to use.

2. I feel that the code needed to find the stubs would add unnecessary complexity ("unpack" core containers, find stubs, etc.)     (Okay, maybe not that complex, but anyway)

3. Simple and readable.

 

By the way; The second time i call synth_design for the full synthesis i am pretty sure that i am not able to skip "elaboration" although i have done elaboration once!? I conclude this after trying and also based on this post https://forums.xilinx.com/t5/Vivado-TCL-Community/Vivado-XDC-and-TCL/td-p/281668/page/2

 

Best regards

Jesper

 

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Xilinx Employee
Xilinx Employee
1,657 Views
Registered: ‎09-20-2012

Re: Infer IP's used in design before calling read_ip

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Hi @jesperjustesen

 

Looks good. Please close the thread by marking the answer if your issue is resolved.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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