cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jlevieux
Adventurer
Adventurer
2,466 Views
Registered: ‎09-12-2007

Inferring Interfaces Adds 77 min to IP Packager Elapsed Time

I have a custom IP core that I package and instantiate into an IPI block design.

 

If I do a simple IP package that just includes the 3 Verilog source files, the TCL script that packages the IP design in non-project mode takes only about 5 seconds of elapsed time.

 

If I infer the 64 user-defined interfaces in addition to the simple IP packaging, the script for the same design increases to 77 minutes in elapsed time.

 

Does this sound like normal expected behavior to increase the elapsed time by such a huge amount for inferring interfaces? I have included the TCL commands below that are used for inferring.

 

If this 77 minute elapsed packaging time is normal operation, is there a way to pre-package the custom IP core so that I do not have to incur the 77 minute delay penalty every time I make a change to the top-level design (in parts of the design outside of the custom IP)?

 

Thanks!
John

 

REFERENCE: Commands used for inferring interface ....
ipx::add_bus_interface $name [ipx::current_core]
set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
set_property interface_mode $mode $m_bus_if
ipx::add_port_map $p_name $m_bus_if
set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]

 

0 Kudos
0 Replies