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Explorer
Explorer
8,316 Views
Registered: ‎02-10-2016

Inout connections in BD

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Hi,

 

The following inout port is created by a TRISTATE_RTL. It is connected to the input port of OBUF. See attached elaboration schematics TRISTATEA and TRISTATEB.  

I have imported both source and destination ports in my BD using write_edif. Source port is an inout port, but cannot connect it to input of OBUF. See attached BD schematic.

I understand why inout ports cannot be connected to buffer inputs. How is this connection possible in the elaboration schematic (not my code), and how can i replicate it in my BD?

 

TIA

Nikos

TRISTATEA.png
TRISTATEb.png
BD.png
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1 Solution

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Explorer
Explorer
16,002 Views
Registered: ‎02-10-2016

Re: Inout connections in BD

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Hi @Austin,

 

Thanks for your reply. That link has little relevance to what I'm doing. Let me ask you this:

 

I do not work with code, just the elaborated schematic of on OOC design (trying to generate a BD from it).

I created an IP for that and imported it to my BD.

 

In the elaboration design the input pin of the internal TRISTATE_RTL is disconnected. So i figured out that although write_edif created external port as IO, in reality it is just an output (write_edif bug?). Since I do not have hierarchy in IPs to control internal RTL structures, I edited the .edn file and changed the IO ports in question to OUTPUT. Regenerated and upgraded the IP.

Is that OK or did i mess things up (have kept an .edn backup)?

 

TIA,

Nikos

 

TIA

Nikos

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5 Replies
Explorer
Explorer
8,314 Views
Registered: ‎02-10-2016

Re: Inout connections in BD

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Actually I figured out how it is done in the elaboration schematic. Only the output port of the 3state RTL is connected to the pin. So the question is:

 

How can i connect the output only of an inout port in BD, to another input?

 

TIA

Nikos

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Scholar austin
Scholar
8,312 Views
Registered: ‎02-27-2008

Re: Inout connections in BD

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Explorer
Explorer
16,003 Views
Registered: ‎02-10-2016

Re: Inout connections in BD

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Hi @Austin,

 

Thanks for your reply. That link has little relevance to what I'm doing. Let me ask you this:

 

I do not work with code, just the elaborated schematic of on OOC design (trying to generate a BD from it).

I created an IP for that and imported it to my BD.

 

In the elaboration design the input pin of the internal TRISTATE_RTL is disconnected. So i figured out that although write_edif created external port as IO, in reality it is just an output (write_edif bug?). Since I do not have hierarchy in IPs to control internal RTL structures, I edited the .edn file and changed the IO ports in question to OUTPUT. Regenerated and upgraded the IP.

Is that OK or did i mess things up (have kept an .edn backup)?

 

TIA,

Nikos

 

TIA

Nikos

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Scholar austin
Scholar
8,240 Views
Registered: ‎02-27-2008

Re: Inout connections in BD

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n,

 

I would say that if the pin is defined as tristate, then it may trim the unused internal node(s), but the tools should not convert it to a different IO.

 

Mistake?  As long as you have no errors, and the design works, then you are done.  Further changes or maintenance on this code may be ugly for the next engineer however, so I would document it (print this thread and place it in the project file).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Explorer
Explorer
8,236 Views
Registered: ‎02-10-2016

Re: Inout connections in BD

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Thanks @Austin,

 

I am still working on my BD. BD is fine with the change, but I can't be sure until I have finished subsequent steps and implementation. I will put a comment about it.

 

I still think that write_edif could have recognized that input pin is unconnected (trimmed) and should have fixed external port accordingly. Otherwise, users will have to edit .edif by hand, as I did, which makes me feel quite uncomfortable.

 

BR,

Nikos

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