06-07-2013 08:45 AM
I'm trying to build a new IP core and want to add an AXI Lite slave interface to it. Searching I found the documentation for the AXI Lite IPIF ( http://www.xilinx.com/products/intellectual-property/axi_lite_ipif.htm ) which seems to be exactly what I need. This core can be found in my Vivado IP catalogue on disk at
but it doesn't appear in the IP catalogue gui and when I try to create an instance of it with the command
create_ip -vendor xilinx.com -library ip -name axi_lite_ipif
I receive the error:
ERROR: [Coretcl 2-1134] No IP matching VLNV 'xilinx.com:ip:axi_lite_ipif:*' was found. Please check your repository configuration.
Further investigation shows that the core is listed in the file /opt/Xilinx/Vivado/2013.1/data/ip/vv_index.xml but it is set as "Hidden" for every architecture. Is there a way for me to instatiate this core even though it's hidden?
(I can make simulation work just by copying the hdl files from the core into my design, but to get synthesis to work I would need to also instantiate the core proc_common v.3.00, which is also hidden).
This seems like a very useful and helpful core for anyone designing their own IP, so I'm wondering why it's hidden.
10-30-2013 09:13 AM
I'm having the exact same problem. I don't find any way to instantiate this core. In EDK this core was instantiated for you when you used the "Create or Import Peripheral" but when using "Create and package IP" in Vivado you only get mapped registers and not the full IPIC interface.
So the question remains, why is it hidden and how is it supposed to be used? I read the PG155 document but it doesn't say anything about it.
Copying it from it's original location into current design folder doesn't feel like the intended way of using it...
03-30-2014 07:31 AM
I have the same problem. This seems to be the only Xilinx interface that fits our need to interface our custom IP. I tried to copy the files of IPIF 2.0 but a lot of packages are missing. I did not find in the Xilinx catalog an axi interface to a generic custom interface containing both memories and control registers. We would appreciate a solution. Thank you, Maurizio
03-31-2014 03:10 AM - edited 03-31-2014 12:36 PM
03-31-2014 11:18 AM
In case you're still having the same problem, I thought I'd mention how I got around it. I modified the .xml files for the two cores that I needed. These are the 'component.xml' files located in the data\ip\xilinx\ repository of Vivado.
04-01-2014 06:05 AM
I looked in the component directory for the IPIC, i modified the attribute hideInCatalogGui to false, it made no difference.
I then modified the vv_index.xml file by changing the part status of the IPIC to production , it was previously Hidden. this then resulted in the part appearing under the IP catalog under the project manage tab, it still does not appear under the IP integrator from the block design window .
I am using 2013.4 which may explain why i am getting different results!
04-07-2014 04:27 PM
I'd encourage you to use the "Create Peripheral" option accessible fromTools->Create and Package IP wizard.
This creates an IP with the same interface logic for axi lite slave (or other AXI interfaces), creating a custom IP which you can then edit and add your own functionality to.
The old IPIC IP had some downsides and most of the feedback was that it would be better for users to incorporate HDL that can perform the AXI transations directly into their custom IP. The above wizard should give you that starting point which you can further edit to incorporate your own functions.
04-08-2014 10:19 PM
I had a similar discussion about "create peripheral" a few days ago. It creates a template which decodes the AXI4-lite bus, but I found that you have to study it and understand it pretty well in order to make use of it, and then modify/circumvent the behavior that they have built in, in order to meet your needs.
The template has areas which say "user logic goes here", etc., but in reality you need to modify many other parts of the module. It seriously needs documentation and examples on how to use it., so that us hapless users don't have to reverse engineer the template functionality.
Also, it creates two HDL modules, where the top one simply calls another one which has an identical interface, and which performs the bus decoding. I still don't understand what is the advantage of this indirection.
06-05-2014 03:23 PM
I don't see "Create and package IP" in Vivado 2013.2, only "package IP". Is it the same thing? Does it need to be invoked from a new project dedicated to the design of this AXI / Custom HDL creation?
09-03-2014 02:04 PM
we are trying to migrate our "old" but working pcores from Planahead 14.2 into Vivado 2014.2. So far this seems linke a real pain. I cant find an easy way to make the pcores usable in vivado. And when I was looking for the essential "AXI Slave Burst" IP that Xilinx proposed at the time of creating the pcores, it seems that we again have to inverst many hours to write a solution for something already solved so many times.
Ever since I startet trying to migrate to vivado I feel like invernting the wheel over and over again. Am I the only one? What easy way am I missing?
What block is replacing the "AXI Slave Burst"?
09-16-2014 11:45 AM
If moving to the new create peripherial code doesn't work for you, another option is to create a library core out of the old pcore source.
This is documented in UG940 Embedded Processor Hardware Design, see "Lab 5: Converting Legacy EDK IP to Use in IP Integrator"
Copy out the old pcore directories from edk and follow along with the lab instructions.