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tahirsengine1
Observer
Observer
170 Views
Registered: ‎06-18-2019

Instantiating block diagram in HDL top

Hey guys,

I received a design project. There is a VHDL top file and there is a block diagram in that project.

The block diagram is instantiated in VHDL.

I had to change block diagram. And now I need to update its instance in VHDL.

The block diagram name is glue.bd

When I use the option "View Instantiation Template", it shows me a file with the module name "glue_wrapper" . But in actual design it is instantiated like

glue_u0 : entity glue

port_map(

...

So how will I update the instance in VHDL file? I can simply add the additional ports in instance, but I really want to do it the proper way.

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1 Reply
syedz
Moderator
Moderator
86 Views
Registered: ‎01-16-2013

@tahirsengine1 

Remove the existing wrapper file from the project and make the modification to block design. After BD validation right-click on .bd file under sources windows and select create HDL wrapper. 

Check topic "Integrating the Block Design into a Top-Level Design" at page 108 in below user guide:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug994-vivado-ip-subsystems.pdf#page=108 

 

--Syed

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