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Visitor jperrin6
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3,582 Views
Registered: ‎01-20-2017

Invalid Parameter Constraint in AXI EPC(2.0) IP

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Using Vivado 2016.4 with a Zync Ultrascale+ target I added an AXI EPC(2.0) to the block design in the IP Integrator. I want to set the peripheral clock to 16MHz but the GUI configuration window for the EPC IP block limits the range of the peripheral clock to 3333 - 41000 ps. I do not see this restriction in the documentation and if I look at the TCL Vivado\2016.4\data\ip\xilinx\axi_epc_v2_0\xgui\axi_epc_v2_0.tcl no validation is actually done on the peripheral clock value (it always returns true and there is commented out code that could do the range validation). 

 

As a quick fix I can modify the Vivado\2016.4\data\ip\xilinx\axi_epc_v2_0\component.xml to change the limit being checked by the GUI and successfully set the clock to 16 MHz.

 

Is this an actual constraint on the IP or a bug in the GUI?

 

Thanks,

Joe

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Visitor jperrin6
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4,444 Views
Registered: ‎01-20-2017

Re: Invalid Parameter Constraint in AXI EPC(2.0) IP

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I had to open a service request to get this answered. The answer is that there is a bug in the IP that Xilinx will not fix so you have to manually edit the IP XML file to remove the incorrect clock constraint. They have not publicly published the answer record that was generated from the SR so you have to contact Xilinx if you want this fix in writing.

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Visitor jperrin6
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4,445 Views
Registered: ‎01-20-2017

Re: Invalid Parameter Constraint in AXI EPC(2.0) IP

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I had to open a service request to get this answered. The answer is that there is a bug in the IP that Xilinx will not fix so you have to manually edit the IP XML file to remove the incorrect clock constraint. They have not publicly published the answer record that was generated from the SR so you have to contact Xilinx if you want this fix in writing.

View solution in original post

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