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Advisor
Advisor
8,803 Views
Registered: ‎02-12-2013

Invisible IP Mystery

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Hello,

 

I am having a lot of trouble adding IP cores to my project in a way that synthesis will see it.

 

In my TCL script that sets up the project I have these commands.

...

read_ip ../ip/fr_rom_3/fr_rom_3.xci

read_ip ../ip/fr_rom_2/fr_rom_2.xci

generate_target {all} [get_ips *]

...

 

Unfortunately, when I run synthesis it tells me

 

ERROR: [Synth 8-493] no such design unit 'fr_rom_3'

 

This is confusing because "report_ip" and "get_ips" both show the cores to be in the project.  Also, if I open the project file in the Vivado GUI it shows the cores correctly located under the vhdl source that calls them.  When I try to run synthesis inside the GUI it instantly replaces the core icons with red question marks and gives the same error message above.

 

Using the GUI, I have found if I remove and then add the xci files a couple of times Vivado will recognize the cores and synthesis can proceed.

 

I have compiled from scripts many times before with IP cores so I don't know why this suddenly stopped working.

 

Any ideas?

 

  Pete

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DSP in hardware and software
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1 Solution

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Xilinx Employee
Xilinx Employee
15,866 Views
Registered: ‎09-20-2012

Re: Invisible IP Mystery

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Hi,

You need to launch IP OOC synthesis run after generating output products of IP.

 

synth_ip [get_ips ip_name]

 

You can use above command to do this.

 

Refer to page-155 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug896-vivado-ip.pdf for more details.


Thanks,
Deepika

Thanks,
Deepika.
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Advisor
Advisor
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Registered: ‎02-12-2013

Re: Invisible IP Mystery

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I should add that the generate_target command is generating a bunch of files like I expected.

I also verified that I am calling the core correctly by looking in the generated .vho file. All the formal parameter have the right names and sizes.
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DSP in hardware and software
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Scholar
Scholar
8,745 Views
Registered: ‎06-05-2013

Re: Invisible IP Mystery

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Hello @pedro_uno ,

 

When you say ip's are getting red question marks i feel cores are generated for some other fpga device and you are trying to use these cores for other fpga family. 

 

is this behaviour consistent? if yes can you attach your script and .xci files to reproduce the issue?

 

 

-Pratham

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Advisor
Advisor
8,737 Views
Registered: ‎02-12-2013

Re: Invisible IP Mystery

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Pratham,

 

Thanks for taking a look at my problem. That was a good idea about wrong families. I double checked the device settings in the IP versus the compilation project and they appear to be the same exact part.

 

I have created a mini-design that shows the problem.  It is attached to this reply.

 

To reproduce the problem just go into the implement folder and run

 

source setup.tcl 

source compile.tcl

 

That should give the error.

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DSP in hardware and software
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Xilinx Employee
Xilinx Employee
15,867 Views
Registered: ‎09-20-2012

Re: Invisible IP Mystery

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Hi,

You need to launch IP OOC synthesis run after generating output products of IP.

 

synth_ip [get_ips ip_name]

 

You can use above command to do this.

 

Refer to page-155 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug896-vivado-ip.pdf for more details.


Thanks,
Deepika

Thanks,
Deepika.
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Advisor
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Registered: ‎02-12-2013

Re: Invisible IP Mystery

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Deepika,

 

That worked.

 

I added this command to my compile script, first thing after opening the project.

 

synth_ip [get_ips *]

 

It identifies when the IP is already synthesized and does not blindly rerun synthesis on the IP each time I compile.

 

This left me wondering how all my other FPGA projects were able to compile.  It looks like some types of IP cores, FIR filters for example, do not need synthesis.  On the other hand, memory IPs need to be individually synthesized.

 

I normally infer or instantiate memories so they can be parameterizable. I guess that is why I never ran into this before.

 

Thanks for the help.

 

  Pete

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DSP in hardware and software
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