UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant saurabhsk
Participant
3,289 Views
Registered: ‎02-17-2009

Issue while running Coregen in batch mode

Hi,

 

 I generated DDR3 model for virtex-6 in verilog. I would like to give a try with batch mode for VHDl now. So I took the mig33.xco file  , which looks like :

 

# BEGIN Project Options

SET addpads = False

SET asysymbol = True

SET busformat = BusFormatParenNotRipped

SET createndf = False

SET designentry = Verilog

SET device = xc6vcx75t

SET devicefamily = virtex6

SET flowvendor = Synplicity

SET formalverification = False

SET foundationsym = False

SET implementationfiletype = Ngc

SET package = ff484

SET removerpms = False

SET simulationfiles = Behavioral

SET speedgrade = -2

SET verilogsim = True

SET vhdlsim = False

# END Project Options

# BEGIN Select

SELECT MIG family Xilinx,_Inc. 3.3

# END Select

# BEGIN Parameters

CSET component_name=mig_33

CSET xml_input_file=/home/mine/ddr3_xcv6_verilog_trial/mig_33/user_design/mig.prj

# END Parameters

GENERATE

# CRC: 511ce836 

 

 As i just want it from verilog to vhdl , so i made this change and run the command:

 

/in/pnrtools/ise_11.4_l68/ixl/ISE/bin/lin/coregen -b mig_33.xco -r -d

 

But it is giving error :

 

WARNING:sim:436 - The selected IP (MIG,3.3) is incompatible with the currently

   selected part.

WARNING:encore:182 - Invalid project options. Family not set.

WARNING:encore:181 - Invalid project options. Device not set.

WARNING:encore:183 - Invalid project options. Package not set.

WARNING:encore:184 - Invalid project options. Speed grade not set.

WARNING:encore:175 - Project options (family='', device='', package='', speed

   grade='') are inconsistent, unavailable or incorrectly entered.

 

Am i missing anything ???

 

Thanks in advance.

 

-Saurabh 

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
3,272 Views
Registered: ‎11-28-2007

Re: Issue while running Coregen in batch mode

You didn't miss anything. Actually the problem is most likely that you have one too many command line option for coregen. Try removing the -r from the command (see below) as it can't be used with the MIG core.

 

coregen -b mig_33.xco -d

 

 

Cheers,
Jim
0 Kudos