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schlee68
Observer
Observer
1,276 Views
Registered: ‎11-13-2017

JESD204_Hardware_Demo

During Generating the Hardware Demo

Stoped In following screen

What is the problem?

 

 screen.jpg

 

I have received in Xilinx web site, following included file

 

 

 

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thakurr
Moderator
Moderator
1,271 Views
Registered: ‎09-15-2016

Hi @schlee68

 

Can you make sure jesd204_0_clocking.v is present in the project directory location?

 

Regards

Rohit

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Regards
Rohit
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balkris
Xilinx Employee
Xilinx Employee
1,252 Views
Registered: ‎08-01-2008

This files should be there in the location 

 

..\JESD204_Hardware_Demo\ac701_hwdemo\jesd204_0_example\jesd204_0_example.srcs\sources_1\imports\example_design\support

Thanks and Regards
Balkrishan
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sschne03
Visitor
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Registered: ‎01-08-2019

I had the same problem when I was running this demo while using Vivado 2018.1.  Because I downloaded the demo for 2015.2 I switched to a remote machine running Vivado 2015.2 and was able to generate the bitstream.  I then copied the bitstream and the debug_nets.LTX file back to my local machine and it appeared to work mostly well, although I am new to the VIO GUI so I can't say that definitively.

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