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techway
Observer
Observer
8,777 Views
Registered: ‎02-17-2012

Kintex 7 IBUFDS_GTE2 & GTX instantiation

Hi all,

 

I try to use a GTX @6.25Gbps (preconfigured as JESD204B link) using a Reference clock at 625MHz (Hardware is like this).

When I configure GTX with GT Wizard in the IP Catalog and when I generate the example design it fails because somewhere in the core a BUFR is used to drive a clock at 625MHz (directly from IBUFDS_GTE2) for logic clocking (cpllreset_wait_reg flip-flops) which is not possible because BUFR is limited to 600MHz in -3 and 540MHz in -2.

 

Th biggest issue is that I can't modify this because it is inside the core generated by the IP Catalog ... So, what is the solution ?

 

Thanks in advance for your support.

pulse_width.PNG
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7 Replies
pulim
Xilinx Employee
Xilinx Employee
8,769 Views
Registered: ‎02-16-2014

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techway
Observer
Observer
8,754 Views
Registered: ‎02-17-2012

Hello,

 

Could you more explicit on how to reroute design after having removing BUFR and replacing it with BUFH.

 

set oldBUFR [get_cells */gtwizard_inst/U0/gtwizard_adc_i/cpll_railing0_i/use_bufr_cpll.refclk_buf]
set newBUFH [create_cell -reference BUFH */gtwizard_inst/U0/gtwizard_adc_i/cpll_railing0_i/use_bufh_cpll.refclk_buf]
connect_net -net [get_nets -of_objects [get_pins $oldBUFR/I]] -objects [get_pins $newBUFH/I]
connect_net -net [get_nets -of_objects [get_pins $oldBUFR/O]] -objects [get_pins $newBUFH/O]
remove_cell $oldBUFR

I basically follow commands above, and it's ok.

But after, I need to place BUFH and Route Nets.

How to do that ?

 

Regards,

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vemulad
Xilinx Employee
Xilinx Employee
8,751 Views
Registered: ‎09-20-2012

Hi @techway

 

You can use create_cell command to create a cell of type BUFH and then use disconnect_net,connect_net commands to replace the BUFR with BUFH. You may remove the BUFR using remove_cell command.

 

After this just run place_design followed by route_design commands. This will place and route in incremental mode.

 

Thanks,

Deepika.

Thanks,
Deepika.
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techway
Observer
Observer
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Registered: ‎02-17-2012

Here is what I do :

set oldBUFR [get_cells -hierarchical  use_bufr_cpll.refclk_buf]
set newBUFH [create_cell -reference BUFH gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/use_bufh_cpll.refclk_buf]
connect_net -net [get_nets -of_objects [get_pins $oldBUFR/I]] -objects [get_pins $newBUFH/I]
connect_net -net [get_nets -of_objects [get_pins $oldBUFR/O]] -objects [get_pins $newBUFH/O]
remove_cell $oldBUFR
place_design

But place fails

 

ERROR: [Place 30-176] Unroutable Placement! The following clock source instance is driving the following locked load instances. The clock source instance is placed too far away from its load instance to be routable. 
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/use_bufh_cpll.refclk_buf (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X1Y64
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32 (SRLC32E.CLK) is provisionally placed by clockplacer on SLICE_X78Y301
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/cpllreset_wait_reg[127] (FDRE.C) is provisionally placed by clockplacer on SLICE_X78Y301
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31 (SRLC32E.CLK) is provisionally placed by clockplacer on SLICE_X78Y301
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/cpllpd_wait_reg[95] (FDRE.C) is provisionally placed by clockplacer on SLICE_X78Y300
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31 (SRLC32E.CLK) is provisionally placed by clockplacer on SLICE_X78Y300
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 (SRLC32E.CLK) is provisionally placed by clockplacer on SLICE_X78Y300
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32 (SRLC32E.CLK) is provisionally placed by clockplacer on SLICE_X78Y300
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32 (SRLC32E.CLK) is provisionally placed by clockplacer on SLICE_X78Y301
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 (SRLC32E.CLK) is provisionally placed by clockplacer on SLICE_X78Y301

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_bufds_bufhce
	Status: PASS 
	Rule Description: A BUFDS driving a BUFH must both be in the same horizontal row (clockregion-wise)
	gtwizard_jesd_support_i/gt_usrclk_source/ibufds_instq2_clk0 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y4
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/cpll_railing0_i/use_bufh_cpll.refclk_buf (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X1Y64

	Clock Rule: rule_bufds_gtxchannel_intelligent_pin
	Status: PASS 
	Rule Description: A BUFDS driving a GTXChannel must both be placed in the same or adjacent clock region
	(top/bottom)
	gtwizard_jesd_support_i/gt_usrclk_source/ibufds_instq2_clk0 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y4
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/gt0_gtwizard_jesd_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y10

	Clock Rule: rule_bufds_gtxcommon_intelligent_pin
	Status: PASS 
	Rule Description: A BUFDS driving a GTXCommon must both be placed in the same or adjacent clock region
	(top/bottom)
	gtwizard_jesd_support_i/gt_usrclk_source/ibufds_instq2_clk0 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y4
	gtwizard_jesd_support_i/common0_i/gtxe2_common_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y2

	Clock Rule: rule_gtxcommon_gtxchannel
	Status: PASS 
	Rule Description: A GTXCommon driving a GTXChannel must both be in the same clock region
	gtwizard_jesd_support_i/common0_i/gtxe2_common_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y2
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/gt0_gtwizard_jesd_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y10

	Clock Rule: rule_gt_bufg
	Status: PASS 
	Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
	gtwizard_jesd_support_i/gtwizard_jesd_init_i/U0/gtwizard_jesd_i/gt0_gtwizard_jesd_i/gtxe2_i (GTXE2_CHANNEL.RXOUTCLK) is locked to GTXE2_CHANNEL_X0Y10
	gtwizard_jesd_support_i/gt_usrclk_source/rxoutclk_bufg0_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y16
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
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techway
Observer
Observer
8,733 Views
Registered: ‎02-17-2012

It's OK now. I replaced the BUFH by a BUFG. Now it is placed and routed.

How can I generate a bistream from that point ?

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vemulad
Xilinx Employee
Xilinx Employee
8,727 Views
Registered: ‎09-20-2012

Hi @techway

 

Yes, from the same session you can use write_bitstream command from tcl console.

 

Thanks,

Deepika.

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
8,644 Views
Registered: ‎09-20-2012

Hi @techway

 

Please close the thread by marking the answer.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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