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Registered: ‎05-13-2011

Kintex UltraScale Custom-Board file: DRC Error for BPI Flash with STARTUPE3

We are having trouble creating working board files for a custom board with a Kintex UltraScale 060 (xcku060-ffva1517-2-e). We use a Micron Flash chip for configuration in Master-BPI mode. The problem occurs because, for our FPGA, some of the Flash pins are placed in Bank 0, which requires going through a STARTUPE3 primitive.

 

We want to use the STARTUPE3 inside the axi_emc core. I created the following "minimal" board files to show what happens. (I also attached them in a ZIP file.)

 

board.xml:

 

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

<board schema_version="2.1" vendor="test" name="test" display_name="Test board" preset_file="preset.xml">
    <compatible_board_revisions><revision id="0">1.0</revision></compatible_board_revisions>
    <file_version>1.0</file_version>
    <description>Test board</description>

    <components>
        <component name="part0" display_name="Kintex UltraScale 060" type="fpga" part_name="xcku060-ffva1517-2-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.xilinx.com/products/silicon-devices/fpga/kintex-ultrascale.html">
            <description>Kintex UltraScale 060</description>
            <interfaces>
                <interface mode="master" name="conf_flash" type="xilinx.com:interface:emc_rtl:1.0" of_component="conf_flash" preset_proc="conf_flash_preset">
                    <preferred_ips>
                        <preferred_ip vendor="xilinx.com" library="ip" name="axi_emc" order="0"/>
                    </preferred_ips>
                    <port_maps>
                        <port_map logical_port="ADDR" physical_port="CONF_FLASH_A" dir="out" left="26" right="1">
                            <pin_maps>
                                <pin_map port_index="1"  component_pin="CONF_FLASH_A1"/>
                                <pin_map port_index="2"  component_pin="CONF_FLASH_A2"/>
                                <pin_map port_index="3"  component_pin="CONF_FLASH_A3"/>
                                <pin_map port_index="4"  component_pin="CONF_FLASH_A4"/>
                                <pin_map port_index="5"  component_pin="CONF_FLASH_A5"/>
                                <pin_map port_index="6"  component_pin="CONF_FLASH_A6"/>
                                <pin_map port_index="7"  component_pin="CONF_FLASH_A7"/>
                                <pin_map port_index="8"  component_pin="CONF_FLASH_A8"/>
                                <pin_map port_index="9"  component_pin="CONF_FLASH_A9"/>
                                <pin_map port_index="10" component_pin="CONF_FLASH_A10"/>
                                <pin_map port_index="11" component_pin="CONF_FLASH_A11"/>
                                <pin_map port_index="12" component_pin="CONF_FLASH_A12"/>
                                <pin_map port_index="13" component_pin="CONF_FLASH_A13"/>
                                <pin_map port_index="14" component_pin="CONF_FLASH_A14"/>
                                <pin_map port_index="15" component_pin="CONF_FLASH_A15"/>
                                <pin_map port_index="16" component_pin="CONF_FLASH_A16"/>
                                <pin_map port_index="17" component_pin="CONF_FLASH_A17"/>
                                <pin_map port_index="18" component_pin="CONF_FLASH_A18"/>
                                <pin_map port_index="19" component_pin="CONF_FLASH_A19"/>
                                <pin_map port_index="20" component_pin="CONF_FLASH_A20"/>
                                <pin_map port_index="21" component_pin="CONF_FLASH_A21"/>
                                <pin_map port_index="22" component_pin="CONF_FLASH_A22"/>
                                <pin_map port_index="23" component_pin="CONF_FLASH_A23"/>
                                <pin_map port_index="24" component_pin="CONF_FLASH_A24"/>
                                <pin_map port_index="25" component_pin="CONF_FLASH_A25"/>
                                <pin_map port_index="26" component_pin="CONF_FLASH_A26"/>
                            </pin_maps>
                        </port_map>
                        <port_map logical_port="DQ_I" physical_port="CONF_FLASH_DQ" dir="in" left="15" right="4">
                            <pin_maps>
                                <pin_map port_index="4"  component_pin="CONF_FLASH_DQ4"/>
                                <pin_map port_index="5"  component_pin="CONF_FLASH_DQ5"/>
                                <pin_map port_index="6"  component_pin="CONF_FLASH_DQ6"/>
                                <pin_map port_index="7"  component_pin="CONF_FLASH_DQ7"/>
                                <pin_map port_index="8"  component_pin="CONF_FLASH_DQ8"/>
                                <pin_map port_index="9"  component_pin="CONF_FLASH_DQ9"/>
                                <pin_map port_index="10" component_pin="CONF_FLASH_DQ10"/>
                                <pin_map port_index="11" component_pin="CONF_FLASH_DQ11"/>
                                <pin_map port_index="12" component_pin="CONF_FLASH_DQ12"/>
                                <pin_map port_index="13" component_pin="CONF_FLASH_DQ13"/>
                                <pin_map port_index="14" component_pin="CONF_FLASH_DQ14"/>
                                <pin_map port_index="15" component_pin="CONF_FLASH_DQ15"/>
                            </pin_maps>
                        </port_map>
                        <port_map logical_port="DQ_O" physical_port="CONF_FLASH_DQ" dir="out" left="15" right="4">
                            <pin_maps>
                                <pin_map port_index="4"  component_pin="CONF_FLASH_DQ4"/>
                                <pin_map port_index="5"  component_pin="CONF_FLASH_DQ5"/>
                                <pin_map port_index="6"  component_pin="CONF_FLASH_DQ6"/>
                                <pin_map port_index="7"  component_pin="CONF_FLASH_DQ7"/>
                                <pin_map port_index="8"  component_pin="CONF_FLASH_DQ8"/>
                                <pin_map port_index="9"  component_pin="CONF_FLASH_DQ9"/>
                                <pin_map port_index="10" component_pin="CONF_FLASH_DQ10"/>
                                <pin_map port_index="11" component_pin="CONF_FLASH_DQ11"/>
                                <pin_map port_index="12" component_pin="CONF_FLASH_DQ12"/>
                                <pin_map port_index="13" component_pin="CONF_FLASH_DQ13"/>
                                <pin_map port_index="14" component_pin="CONF_FLASH_DQ14"/>
                                <pin_map port_index="15" component_pin="CONF_FLASH_DQ15"/>
                            </pin_maps>
                        </port_map>
                        <port_map logical_port="DQ_T" physical_port="CONF_FLASH_DQ" dir="out" left="15" right="4">
                            <pin_maps>
                                <pin_map port_index="4"  component_pin="CONF_FLASH_DQ4"/>
                                <pin_map port_index="5"  component_pin="CONF_FLASH_DQ5"/>
                                <pin_map port_index="6"  component_pin="CONF_FLASH_DQ6"/>
                                <pin_map port_index="7"  component_pin="CONF_FLASH_DQ7"/>
                                <pin_map port_index="8"  component_pin="CONF_FLASH_DQ8"/>
                                <pin_map port_index="9"  component_pin="CONF_FLASH_DQ9"/>
                                <pin_map port_index="10" component_pin="CONF_FLASH_DQ10"/>
                                <pin_map port_index="11" component_pin="CONF_FLASH_DQ11"/>
                                <pin_map port_index="12" component_pin="CONF_FLASH_DQ12"/>
                                <pin_map port_index="13" component_pin="CONF_FLASH_DQ13"/>
                                <pin_map port_index="14" component_pin="CONF_FLASH_DQ14"/>
                                <pin_map port_index="15" component_pin="CONF_FLASH_DQ15"/>
                            </pin_maps>
                        </port_map>
                        <port_map logical_port="ADV_LDN" physical_port="CONF_FLASH_ADV_N" dir="out">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="CONF_FLASH_ADV_N"/>
                            </pin_maps>
                        </port_map>
                        <port_map logical_port="OEN" physical_port="CONF_FLASH_OE_N" dir="out">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="CONF_FLASH_OE_N"/>
                            </pin_maps>
                        </port_map>
                        <port_map logical_port="WEN" physical_port="CONF_FLASH_WE_N" dir="out">
                            <pin_maps>
                                <pin_map port_index="0" component_pin="CONF_FLASH_WE_N"/>
                            </pin_maps>
                        </port_map>
                    </port_maps>
                </interface>
            </interfaces>
        </component>

        <component name="conf_flash" display_name="Configuration Flash" type="chip" sub_type="memory_flash_bpi" major_group="External Memory" part_name="PC28F00AG18F" vendor="Micron" spec_url="www.micron.com/~/media/documents/products/data-sheet/nor-flash/parallel/g18/256_512_1gb_g18_it.pdf">
            <description>128 MB configuration-data Flash (MT28GU01GAAA1EGC-0SIT)</description>
        </component>
    </components>

    <jtag_chains>
        <jtag_chain name="chain1">
            <position name="0" component="part0"/>
        </jtag_chain>
    </jtag_chains>

    <connections>
        <connection name="part0_conf_flash" component1="part0" component2="conf_flash">
            <connection_map name="part0_conf_flash_map" c1_st_index="0" c1_end_index="40" c2_st_index="0" c2_end_index="40"/>
        </connection>
    </connections>
</board>

 

part0_pins.xml:

 

<?xml version="1.0" encoding="UTF-8" standalone="no"?>

<part_info part_name="xcku060-ffva1517-2-e">
    <pins>
        <!-- The DQ0, DQ1, DQ2, DQ3, CE_N, CLK, and RST_N pins are connected to bank 0 and only accessible through STARTUPE3 -->
        <pin index="0" name="CONF_FLASH_A1"  iostandard="LVCMOS18" loc="AJ15" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="1" name="CONF_FLASH_A2"  iostandard="LVCMOS18" loc="AK15" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="2" name="CONF_FLASH_A3"  iostandard="LVCMOS18" loc="AH14" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="3" name="CONF_FLASH_A4"  iostandard="LVCMOS18" loc="AJ14" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="4" name="CONF_FLASH_A5"  iostandard="LVCMOS18" loc="AL14" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="5" name="CONF_FLASH_A6"  iostandard="LVCMOS18" loc="AL13" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="6" name="CONF_FLASH_A7"  iostandard="LVCMOS18" loc="AL12" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="7" name="CONF_FLASH_A8"  iostandard="LVCMOS18" loc="AM12" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="8" name="CONF_FLASH_A9"  iostandard="LVCMOS18" loc="AM14" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="9" name="CONF_FLASH_A10" iostandard="LVCMOS18" loc="AN14" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="10" name="CONF_FLASH_A11" iostandard="LVCMOS18" loc="AN13" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="11" name="CONF_FLASH_A12" iostandard="LVCMOS18" loc="AN12" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="12" name="CONF_FLASH_A13" iostandard="LVCMOS18" loc="AP14" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="13" name="CONF_FLASH_A14" iostandard="LVCMOS18" loc="AP13" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="14" name="CONF_FLASH_A15" iostandard="LVCMOS18" loc="AR12" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="15" name="CONF_FLASH_A16" iostandard="LVCMOS18" loc="AT12" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="16" name="CONF_FLASH_A17" iostandard="LVCMOS18" loc="AP15" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="17" name="CONF_FLASH_A18" iostandard="LVCMOS18" loc="AR15" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="18" name="CONF_FLASH_A19" iostandard="LVCMOS18" loc="AR13" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="19" name="CONF_FLASH_A20" iostandard="LVCMOS18" loc="AT13" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="20" name="CONF_FLASH_A21" iostandard="LVCMOS18" loc="AT14" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="21" name="CONF_FLASH_A22" iostandard="LVCMOS18" loc="AU14" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="22" name="CONF_FLASH_A23" iostandard="LVCMOS18" loc="AU12" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="23" name="CONF_FLASH_A24" iostandard="LVCMOS18" loc="AV12" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="24" name="CONF_FLASH_A25" iostandard="LVCMOS18" loc="AT15" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="25" name="CONF_FLASH_A26" iostandard="LVCMOS18" loc="AU15" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="26" name="CONF_FLASH_ADV_N" iostandard="LVCMOS18" loc="AL15" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="27" name="CONF_FLASH_DQ4"  iostandard="LVCMOS18" loc="AF14" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="28" name="CONF_FLASH_DQ5"  iostandard="LVCMOS18" loc="AG14" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="29" name="CONF_FLASH_DQ6"  iostandard="LVCMOS18" loc="AE13" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="30" name="CONF_FLASH_DQ7"  iostandard="LVCMOS18" loc="AF13" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="31" name="CONF_FLASH_DQ8"  iostandard="LVCMOS18" loc="AF15" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="32" name="CONF_FLASH_DQ9"  iostandard="LVCMOS18" loc="AG15" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="33" name="CONF_FLASH_DQ10" iostandard="LVCMOS18" loc="AG12" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="34" name="CONF_FLASH_DQ11" iostandard="LVCMOS18" loc="AH12" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="35" name="CONF_FLASH_DQ12" iostandard="LVCMOS18" loc="AK13" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="36" name="CONF_FLASH_DQ13" iostandard="LVCMOS18" loc="AK12" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="37" name="CONF_FLASH_DQ14" iostandard="LVCMOS18" loc="AH13" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="38" name="CONF_FLASH_DQ15" iostandard="LVCMOS18" loc="AJ13" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
        <pin index="39" name="CONF_FLASH_OE_N" iostandard="LVCMOS18" loc="AV16" drive="12" slew="SLOW"/>
        <pin index="40" name="CONF_FLASH_WE_N" iostandard="LVCMOS18" loc="AW16" drive="12" output_impedance="RDRV_NONE_NONE" slew="SLOW"/>
    </pins>
</part_info>

 

preset.xml:

 

<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<ip_presets schema="1.0">
    <ip_preset preset_proc_name="conf_flash_preset">
        <ip vendor="xilinx.com" library="ip" name="axi_emc">
            <user_parameters>
                <user_parameter name="CONFIG.C_MAX_MEM_WIDTH" value="16" />
                <user_parameter name="CONFIG.C_MEM0_TYPE" value="2" />
                <user_parameter name="CONFIG.C_MEM0_WIDTH" value="16" />
                <user_parameter name="CONFIG.C_TCEDV_PS_MEM_0" value="96000" /> <!-- t_ELQV -->
                <user_parameter name="CONFIG.C_TAVDV_PS_MEM_0" value="96000" /> <!-- t_AVQV -->
                <user_parameter name="CONFIG.C_TPACC_PS_FLASH_0" value="15000" /> <!-- t_APA -->
                <user_parameter name="CONFIG.C_THZCE_PS_MEM_0" value="7000" /> <!-- t_EHQZ -->
                <user_parameter name="CONFIG.C_THZOE_PS_MEM_0" value="7000" /> <!-- t_GHQZ -->
                <user_parameter name="CONFIG.C_TWC_PS_MEM_0" value="40000" /> <!-- t_CW = t_ELWL + t_WLWH + t_WHEH -->
                <user_parameter name="CONFIG.C_TWP_PS_MEM_0" value="40000" /> <!-- t_WP = t_WLWH -->
                <user_parameter name="CONFIG.C_TWPH_PS_MEM_0" value="20000" /> <!-- t_WHWL -->
                <user_parameter name="CONFIG.C_TLZWE_PS_MEM_0" value="20000" /> <!-- t_WHGL (incl. READ STATUS after status-register change) -->
                <user_parameter name="CONFIG.C_WR_REC_TIME_MEM_0" value="30000" /> <!-- Not sure, assume t_WHQV - t_AVQV -->
                <user_parameter name="CONFIG.C_USE_STARTUP" value="1" />
                <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1" />
            </user_parameters>
        </ip>
    </ip_preset>
</ip_presets>

 

I use these to create a new project in Vivado 2017.3. I make a Block Design and try to add the "Configuration Flash" from the Board tab. This leads to the following error:

 

 

ERROR: [IP_Flow 19-3461] Value '12' is out of the range for parameter 'Maximum Data Width of Memories(C_MAX_MEM_WIDTH)' for BD Cell 'axi_emc_0' . Valid values are - 8, 16, 32, 64
INFO: [IP_Flow 19-3438] Customization errors found on 'axi_emc_0'. Restoring to previous valid configuration.
ERROR: [BD 41-245] set_property error - Value '12' is out of the range for parameter 'Maximum Data Width of Memories(C_MAX_MEM_WIDTH)' for BD Cell 'axi_emc_0' . Valid values are - 8, 16, 32, 64
Customization errors found on 'axi_emc_0'. Restoring to previous valid configuration.

It seems to me that a DRC check in axi_emc doesn't like that the DQ port only has 12 bytes, because the lower 4 ones are connected to the STARTUPE3 internally. This check doesn't seem to happen when I manually add an axi_emc with C_USE_STARTUP_INT=1 in the Block Design, only when I use the interface.

 

 

I have tried to make the port have 16 bits, but then the board file doesn't work at all, unless I have loc constraints for all pins in part0_pins.xml. If I add the locations there, it doesn't work either. What seems to happen is that all constraints seem to shift down 4 positions.

 

I also tried to set C_USE_STARTUP_INT=0 to instantiate the STARTUPE3 in the wrapper file. However, then I'd have to divide the DQ bus into 12 bits assigned to pins and 4 bits connected to signals. I could find a way to do this, either.

 

There doesn't seem to be a Xilinx board with a BPI Flash that requires STARTUPE3, so I cannot copy anything from the examples. I'm wondering if this is a tool issue, or if I'm missing something.

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Registered: ‎05-13-2011

Re: Kintex UltraScale Custom-Board file: DRC Error for BPI Flash with STARTUPE3

If somebody with more insight into the inner workings of board XML files could have a look at this, that would be very much appreciated. I provided a complete test case that consistently causes the error in 2017.3, and in which I cannot find anything wrong according to UG895.

 

For now, I can only assume that this is a software bug that prevents us from creating working XML files for our board.

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Registered: ‎05-13-2011

Re: Kintex UltraScale Custom-Board file: DRC Error for BPI Flash with STARTUPE3

The support for STARTUPE3, added to the axi_emc core Version 3.0 (Rev. 6) (Vivado 2015.3), is incomplete.

 

The option to use the internal STARTUPE3 works with Custom board interfaces, but not with interfaces specified in board-support files. The reason this hasn't come up is that there are no Xilinx boards that require this option.

 

When the internal STARTUPE3 is used, the rightmost four bits of the data-bus vector are internally connected to the primitive. Therefore, they cannot be routed to the external DQ pins, which then span, i.e., (15 downto 4) instead of (15 downto 0).

 

The problem is in the parameter C_MAX_MEM_WIDTH. This must be one of 8, 16, 32, and 64. It specifies the leftmost bit position of the DQ vector. The rightmost bit position is given by C_PORT_DIFF, which is correctly set to 4 when C_USE_STARTUP_INT is 1, otherwise to 0. When a board-support file is used, however, the TCL process update_PARAM_VALUE.C_MAX_MEM_WIDTH in xgui/axi_emc_v3_0.tcl sets the value of C_MAX_MEM_WIDTH directly from the number of external DQ pins found in the board files

 

This setting doesn't take into account the possibility that C_USE_STARTUP_INT is 1, in which case the width of the DQ vector is 4 smaller than the actual data width. Hence C_MAX_MEM_WIDTH gets an invalid value like 12, which leads to a DRC error.

 

I tried to add support to xgui/axi_emc_v3_0.tcl with a patch like this:

892c892
< proc update_PARAM_VALUE.C_MAX_MEM_WIDTH { PARAM_VALUE.C_MAX_MEM_WIDTH PARAM_VALUE.EMC_BOARD_INTERFACE PARAM_VALUE.C_MEM0_WIDTH PARAM_VALUE.C_MEM1_WIDTH PARAM_VALUE.C_MEM2_WIDTH PARAM_VALUE.C_MEM3_WIDTH PARAM_VALUE.C_NUM_BANKS_MEM} {
---
> proc update_PARAM_VALUE.C_MAX_MEM_WIDTH { PARAM_VALUE.C_MAX_MEM_WIDTH PARAM_VALUE.EMC_BOARD_INTERFACE PARAM_VALUE.C_MEM0_WIDTH PARAM_VALUE.C_MEM1_WIDTH PARAM_VALUE.C_MEM2_WIDTH PARAM_VALUE.C_MEM3_WIDTH PARAM_VALUE.C_NUM_BANKS_MEM PARAM_VALUE.C_USE_STARTUP_INT } {
904a905,908
>            set c_use_startup_int [ get_property value ${PARAM_VALUE.C_USE_STARTUP_INT} ]
>            if {$c_use_startup_int == 1} {
>                set dataWidth [expr {$dataWidth + 4}]
>            }

The only problem is that update_PARAM_VALUE.C_MAX_MEM_WIDTH seems to be called once before init_params. That means that C_USE_STARTUP_INT is not yet set, and the value of C_MAX_MEM_WIDTH is not increased. Therefore the patch doesn't help.

 

It would be nice if support for this were added in future core versions, and a working patch were published. The way the core TCL files work doesn't seem to be very well documented anywhere.

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Re: Kintex UltraScale Custom-Board file: DRC Error for BPI Flash with STARTUPE3

For the time being, I use the following patch for xgui/axi_emc_v3_0.tcl. It rounds up the detected width of C_MAX_MEM_WIDTH to the next legal value. It's dirty, so I don't consider this a solution. I hope it will be fixed in a future Vivado / axi_emc version.

904a905,913
>            if {$dataWidth > 32} {
>                set dataWidth 64
>            } elseif {$dataWidth > 16} {
>                set dataWidth 32
>            } elseif {$dataWidth > 8} {
>                set dataWidth 16
>            } else {
>                set dataWidth 8
>            }
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Re: Kintex UltraScale Custom-Board file: DRC Error for BPI Flash with STARTUPE3

The issue is still present in Vivado 2018.1. The same patch still works.

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Re: Kintex UltraScale Custom-Board file: DRC Error for BPI Flash with STARTUPE3

The issue is still present in Vivado 2018.2. The same patch still works.

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Re: Kintex UltraScale Custom-Board file: DRC Error for BPI Flash with STARTUPE3

The issue is still present in Vivado 2019.1. The same patch still works.

It would be very much appreciated if a fix could be integrated in the mainline Vivado version, so that we don't need to patch every single version ourselves. The error is easy to reproduce with the originally attached files, and I posted a working patch almost two years ago, after which several unrelated revisions were made to the core.

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Contributor
Contributor
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Registered: ‎05-13-2011

Re: Kintex UltraScale Custom-Board file: DRC Error for BPI Flash with STARTUPE3

Vivado 2019.2 still has this bug.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

Re: Kintex UltraScale Custom-Board file: DRC Error for BPI Flash with STARTUPE3

Thanks for the updates.  First time I saw this post sadly.  I am pretty familiar with board.xml so I'll take look early next week.  Sorry for the trouble you have been having with making board files.

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