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Scholar muravin
Scholar
6,977 Views
Registered: ‎11-21-2013

LOC errors on KC705 GPIOs

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Hi All,

 

Never had this problem and never seen anything like this before.

 

We are using a GPIO for LEDs on the KC705. Customization is done for LEDs but bitgen gives the following error (see below, at the bottom of the post). I tried adding LOC constraint manually as following, per KC705 user guide, but this makes no difference. Same for the I/O standard. The project settings, board part set to KC705 1.2. Can someone please tell me what can cause this error?

 

Thanks

Vlad

 

set_property PACKAGE_PIN AB8  [get_ports led_8bits_tri_o[0]  ]
set_property PACKAGE_PIN AA8  [get_ports led_8bits_tri_o[1]  ]
set_property PACKAGE_PIN AC9  [get_ports led_8bits_tri_o[2]  ]
set_property PACKAGE_PIN AB9  [get_ports led_8bits_tri_o[3]  ]
set_property PACKAGE_PIN AA26 [get_ports led_8bits_tri_o[4]  ]
set_property PACKAGE_PIN G19  [get_ports led_8bits_tri_o[5]  ]
set_property PACKAGE_PIN E18  [get_ports led_8bits_tri_o[6]  ]
set_property PACKAGE_PIN F16  [get_ports led_8bits_tri_o[7]  ]

 

[DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 4 out of 291 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: led_8bits_tri_o[7:0].

Vladislav Muravin
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1 Solution

Accepted Solutions
Historian
Historian
13,576 Views
Registered: ‎01-23-2009

Re: LOC errors on KC705 GPIOs

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For whatever reason, something is wrong with the pin constraints - even though they look correct, there must be something wrong with them.

 

Are you using project mode, or non-project batch? I will assume project mode...

 

What do you mean by "manually" - did you type these commands into the Tcl prompt in the GUI? If so, are you sure you let the tools write your XDC file out - these properties are not applied to the netlist, but to the constraints, which need to be read in at the next (or any subsequent) stage of the process. When did you apply them? After synthesis? Give us more information about exactly what you did.

 

If they did make it into the XDC file before implementation (which is when they are needed), then make sure they are getting read in properly - look at the log file during implementation and see if there are any warnings/errors when the XDC file is read in.

 

It is interesting that it appears to be only 4 pins. One oddity of the KC705 board is that the LEDs are in  different I/O banks with two different I/O standards; led[3:0] are in bank 33 with a voltage of 1.5, whereas led[7:4] are in banks 13, 17, and 18 with a voltage of 2.5. Maybe your IOSTANDARDs are not consistent on some of them which is causing them to be discarded (which shouldn't happen, but...)

 

Avrum

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3 Replies
Historian
Historian
13,577 Views
Registered: ‎01-23-2009

Re: LOC errors on KC705 GPIOs

Jump to solution

For whatever reason, something is wrong with the pin constraints - even though they look correct, there must be something wrong with them.

 

Are you using project mode, or non-project batch? I will assume project mode...

 

What do you mean by "manually" - did you type these commands into the Tcl prompt in the GUI? If so, are you sure you let the tools write your XDC file out - these properties are not applied to the netlist, but to the constraints, which need to be read in at the next (or any subsequent) stage of the process. When did you apply them? After synthesis? Give us more information about exactly what you did.

 

If they did make it into the XDC file before implementation (which is when they are needed), then make sure they are getting read in properly - look at the log file during implementation and see if there are any warnings/errors when the XDC file is read in.

 

It is interesting that it appears to be only 4 pins. One oddity of the KC705 board is that the LEDs are in  different I/O banks with two different I/O standards; led[3:0] are in bank 33 with a voltage of 1.5, whereas led[7:4] are in banks 13, 17, and 18 with a voltage of 2.5. Maybe your IOSTANDARDs are not consistent on some of them which is causing them to be discarded (which shouldn't happen, but...)

 

Avrum

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Scholar muravin
Scholar
6,964 Views
Registered: ‎11-21-2013

Re: LOC errors on KC705 GPIOs

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Thanks Avrum for prompt response. We are using project mode, and this is or 3rd project with KC705. By "manually" I meant that I simply added the constraints into the XDC file while I know I don't have to because they are part of the board-specific properties assigned to the IP.

I will have to review the I/O standards.

BR
Vlad
Vladislav Muravin
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Scholar muravin
Scholar
6,948 Views
Registered: ‎11-21-2013

Re: LOC errors on KC705 GPIOs

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That was the issue Avrum. I am suprised that this is the 3rd project we run with KC705 and the previous two were not reporting this error.

Thanks again for the help.

Vladislav Muravin
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