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Participant
Participant
269 Views
Registered: ‎06-11-2019

LUT design

Hello

Can someone please tell how to write verilog code for a look up table in vivado with 9 inputs and 1 output.

Like should the verilog code for LUT be written in a different module and then called in the main module ?

Is there any syntax or format to write verilog code for LUT ?

Looking forward for the response at the earliest.

Thank you

 

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Teacher
Teacher
260 Views
Registered: ‎07-09-2009

Re: LUT design

be aware, a LUT is a special name in Xilinx world,

Also be aware that universities monitor this site for homework questions being posted.

 

this is just a simple 9 element rom.

 

look at page 237.  the case statment.

https://www.csee.umbc.edu/~tinoosh/cmpe415/slides/Rom-LUT-verilog.pdf

,

 

 

 

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