Can someone please tell how to write verilog code for a look up table in vivado with 9 inputs and 1 output.
Like should the verilog code for LUT be written in a different module and then called in the main module ?
Is there any syntax or format to write verilog code for LUT ?
Looking forward for the response at the earliest.
be aware, a LUT is a special name in Xilinx world,
Also be aware that universities monitor this site for homework questions being posted.
this is just a simple 9 element rom.
look at page 237. the case statment.