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Visitor
Visitor
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Registered: ‎06-06-2018

Language Templates

Hi,

I just had a look at Vivado 2019.1 Language Templates VHDL section and got the impression that some items should be updated. What I Just found:

  • Utilization of process for  register (aka non combinatorial) logic generation: IMHO the old fashioned construct like "if (<clock>'event and <clock> = '1') then" should be substituted with "if rising_edge(<clock>) then" accordingly on all occurences (synthesis and simulation, negedge and posedge).  In VHDL/Synthesis Constructs/Process/Process/(Negedge | Posedge) Clock all lines beginning with "if (clock'event " contain a superfluous ">" before the closing ")".
  • In VHDL/Synthesis Constructs/Attributes/Synthesis/Finite State-Machine/FSM Encoding/One-hot the encoding for "one hot" given in the examples is wrong: IMHO is must be "one_hot" and not "one-hot" (as far as I rembember the latter was used with ISE).

 

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Teacher
Teacher
202 Views
Registered: ‎07-09-2009

Re: Language Templates

Oh yes,

 

the templates are shocking , especialy for VHDL.

   They always looked like they were generated by a student from a book,

      and they have not been updated for decades,   still using 87 code rules I think.

 

But, hay

 

Xilxin dont activly support VHDL, they are mainly Verilog,

    look at the large number of exapmles, or the test benches provided that are only in Verilog now,

       so don't expect to much ,

 

 

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