I just had a look at Vivado 2019.1 Language Templates VHDL section and got the impression that some items should be updated. What I Just found:
Utilization of process for register (aka non combinatorial) logic generation: IMHO the old fashioned construct like "if (<clock>'event and <clock> = '1') then" should be substituted with "if rising_edge(<clock>) then" accordingly on all occurences (synthesis and simulation, negedge and posedge). In VHDL/Synthesis Constructs/Process/Process/(Negedge | Posedge) Clock all lines beginning with "if (clock'event " contain a superfluous ">" before the closing ")".
In VHDL/Synthesis Constructs/Attributes/Synthesis/Finite State-Machine/FSM Encoding/One-hot the encoding for "one hot" given in the examples is wrong: IMHO is must be "one_hot" and not "one-hot" (as far as I rembember the latter was used with ISE).