Limit the scope of IP constraints

[ddfst]

Hello,

I have packaged my IP along with its constraints (such as input clock frequency).

When I implement my design using that IP all the constraints from the IP apply as project global constraints and I end up having duplicate constraints describing the same clock (one is from project constraints, another from IP constraints) and timing analysis thinks these are dirrefent clocks.

I have noticed Xilinx IPs from the IP catalog do not act like that, they also have input clock constraints but they don't end up in extra clocks appearing in timing analysis as this input clock is already constrained by project XDC.

How can I make my IP constraints act the same way?

[graces · Accepted solution]

Constraints can be scoped to a specific module, to specific cells of your design, or both, if needed. This is achieved by setting COPED_TO_REF/COPED_TO_CELLS property to .xdc.

For more details, please have a look at UG903, pg67, section "Constraints Scoping".

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug903-vivado-using-constraints.pdf