10-22-2019 03:39 AM
Is it possible to write logic (FIFOs, etc) inside of SystemVerilog Interfaces?
Could a logic be written inside of modports?
10-22-2019 04:51 AM
Hi @ldm_as ,
Please check the below post on how to connect interface to logic in Vivado synthesi:
10-22-2019 11:21 AM
The referenced article does not address @ldm_as root question.
The root question is active logic inside of a SystemVerilog interface. Within a modport is not the correct question, it's actually within the interface. A modport (apart from giving a hint to tools regarding port directions) only restricts access to the entire interface members. By accessing interface members via a modport, you're just restricting yourself to a limited subset of the entire interface. This can be ok, analogous to public/private methods in OO design.
Back to the original question - active logic within interfaces. The language restricts your somewhat - one cannot instantiate sub-module instances within an interface. The language does allow procedural blocks (always, initial), and continuous assignments within an interface. However, my experiments with Vivado Synthesis in this regard have shown LIMITED support. The tool often would accept legal SystemVerilog code within an interface, but NOT produce logic which matched the RTL. The tool may also (falsely) trigger with weird multi-driver error messages. In short, no Vivado doesn't appear to support active logic within an interface.
Functions within an interface that sample the interface members are supported, and work in well in synthesis, and can be modport imported into the calling modules scope. We use these extensively.
10-23-2019 02:09 AM
"Functions ... can be modport imported into the calling modules scope" - could you please explain what does it mean "imported"? Could you please provide an example?
10-23-2019 08:36 AM
interface some_bus_if(); bit [ 31 : 0 ] bus_addr;
function bit match_addr( input bit [ 31 : 0 ] my_reg_addr, my_reg_range );
if( some_calc_of( my_reg_addr, my_reg_range, bus_addr ) )
match = 1;
return( match );
/* port direction modports here */,
// other module sigals
wire my_reg_matches_bus_cycle = s_my_bus_if.match_addr( my_reg_addr, my_reg_reg_range );
// above wire is a one when a bus operation is occuring to this register's decode range