cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
nlotankar
Visitor
Visitor
618 Views
Registered: ‎11-14-2019

MIG 2.2 v6 - WID signal missing in AXI write data channel

Jump to solution

Hi,

I am trying to use DDR4 SDRAM ( MIG 2.2 v6 ) in Vivado IP Integrator. The problem I am facing is in AXI interface of MIG where 4-bit ID signal is present for all the transaction channels except for write data channel (WID). 

My goal is to interface it with a custom IP that I have imported, which has WID signal present in it.

Any help will be appreciated.

Thanks,

Ninad L

0 Kudos
1 Solution

Accepted Solutions
nlotankar
Visitor
Visitor
561 Views
Registered: ‎11-14-2019

Sorry, my bad. It seems I am lazy enough to not go through AXI4 documents.

It says, write interleaving is not supported in AXI4, which is the reason here for WID signal being mysteriously vanished.

View solution in original post

axi4.JPG
0 Kudos
3 Replies
syedz
Moderator
Moderator
602 Views
Registered: ‎01-16-2013

@nlotankar 

 

Can you share the snapshot from block design and highlight the signals which you mentioned? Also share device and vivado version you are using.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
nlotankar
Visitor
Visitor
596 Views
Registered: ‎11-14-2019

I have highlighted all the axi id signals present in DDR4 IP. I can't find a similar id signal for write data channel.

 

Device : xcvu440-flga2892-1-c

Vivado : v2018.3

ddr4.JPG
0 Kudos
nlotankar
Visitor
Visitor
562 Views
Registered: ‎11-14-2019

Sorry, my bad. It seems I am lazy enough to not go through AXI4 documents.

It says, write interleaving is not supported in AXI4, which is the reason here for WID signal being mysteriously vanished.

View solution in original post

axi4.JPG
0 Kudos