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tembridis.com
Explorer
Explorer
4,235 Views
Registered: ‎07-14-2008

MIG 3.2 and Virtex6. Need clarification

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Good morning,

 

my PLB layouter has a certain problem, here's the deal:

 

We plan on using XC6VLX75T-FF784 for our next project. Our layouter (as per usual) wants to cram the pins for DDR into the least number of banks possible. Actually, for two seperate DDR controller. However, he is running short a few pins per bank and asked me to find out about this three signals:

 

  • phy_init_done
  • sys_rst
  • error

 

I was under the impression that the init done signal had no effect on any external hardware, but I am not quite sure. In #AR33407 there is a side note that says:


"The issue is with the System Control group which includes the phy_init_done, sys_rst, and error signals. Note, in most user designs, these signals are not pulled out to I/O and so selecting a different bank for this group and leaving Address/Control in the desired FPGA bank is not a concern."

 

Now, could someone please clarify if these pins are needed at all.

 

Thanks in advance and best regards.

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jschmitz
Xilinx Employee
Xilinx Employee
4,824 Views
Registered: ‎10-23-2007
You can most likely supply or monitor these signals internally and do not need pins for them.  "phy_init_done" tells you when the controller is done calibrating, so you want to use this to determine when the controller is available for use.  You most likely don't need a pin for it.  You do need to reset the controller via "sys_rst", but this doesn't need to be from a pin - your own internal reset signal is likley sufficient.  And "error" is only used with the example design's synthesizable testbench.  If you don't use the testbench, you don't need this, and in any case you can route this signal anywhere you want as long as you have a way to monitor it if you do use the testbench.

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jschmitz
Xilinx Employee
Xilinx Employee
4,825 Views
Registered: ‎10-23-2007
You can most likely supply or monitor these signals internally and do not need pins for them.  "phy_init_done" tells you when the controller is done calibrating, so you want to use this to determine when the controller is available for use.  You most likely don't need a pin for it.  You do need to reset the controller via "sys_rst", but this doesn't need to be from a pin - your own internal reset signal is likley sufficient.  And "error" is only used with the example design's synthesizable testbench.  If you don't use the testbench, you don't need this, and in any case you can route this signal anywhere you want as long as you have a way to monitor it if you do use the testbench.

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