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Registered: ‎11-19-2019

MIG 7 Series IP Generation Issue


Vivado 2017.2.1 & 2019.2 on 18.04.2 LTS via VirtualBox 6.1.0

Arty Rev. C.0 (XC7A35TICSG324-1L with DDR3 MT41J128M16JT-125:K)



I'm trying to bring up a basic hello world using Arty, following a tutorial by Adam Taylor (link, link). In the block design flow, performing a drag and drop from the board tab to the design canvas results in the following error (full log attached) in both Vivado 2017.2.1 and 2019.2.

ERROR: [IP_Flow 19-3475] Tcl error in ::ipgui_ar_bp_mig_7series_0_0::updateAllModelParams procedure for BD Cell 'mig_7series_0'. couldn't open "<path>/mig.v": no such file or directory

Vivado adds the block to the canvas, but it's restored to a valid configuration (same as using the Add IP button). In Adam's video, he shows that all customization presets are pre-applied when using the drag and drop.

I have consulted AR54025, AR71898, AR66722. The current MIG 7 series tactical patch is only usable with Vivado 2018.3 and in AR71898 this issue I'm seeing isn't listed to be a supported fix.

A similar issue is described here. Should I manually edit the Tcl script which generates the MIG IP? If so, what changes should I apply?

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2 Replies
Registered: ‎01-16-2013

Re: MIG 7 Series IP Generation Issue 


I tried this with AC701 board and I do not see any issue in adding DDR3 to block design from boards tab. The presets are getting applied. Can you try with the same board and check?


Can you share the vivado.log file? Try reducing the project directory path and check.



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Registered: ‎11-19-2019

Re: MIG 7 Series IP Generation Issue

Hi Syed,

Thank you for your suggestion. I've tried the same process for ac701 and received the same error (vivado.log attached).

File path length is only a Windows issue, right? Since this is failing for Arty and ac701, I'm more inclined to think it's a linux-specific issue.

For the error, the file in question does exist, though Vivado claims it doesn't.




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