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Observer hkassir72
Observer
167 Views
Registered: ‎12-07-2015

Minimal AXI Interface with Burst Support

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Hello,

I want to instantiate an AXI slave that supports burst reads/writes.

What is the minimal list of ports I must have in order to connect my block to an AXI master through an AXI Interconnect. I know that the user ports can be dropped. But can I also drop ID, Lock, Cache, Protection, Region, and QoS ports?

And what do the attributes (HAS_CACHE, HAS_LOCK, HAS_PROT, HAS_QOS, HAS_REGION) indicate exactly? From my understanding, they mean that I must declare the ports, but the attribute indicates that the Master doesn't have to drive the signals (which kind of answers the first question but I would like to verify).

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Observer hkassir72
Observer
111 Views
Registered: ‎12-07-2015

Re: Minimal AXI Interface with Burst Support

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I tested a system with MPSOC Zynq Ultrascale+ ARM processed as a master. It seems that the only necessary full AXI port to support bursts is the ID (aside from burst length and size, of course).

I could safely synthsize and run an AXI bus without Lock, Cache, Protection, Region, and QoS ports.

 

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Observer hkassir72
Observer
112 Views
Registered: ‎12-07-2015

Re: Minimal AXI Interface with Burst Support

Jump to solution

I tested a system with MPSOC Zynq Ultrascale+ ARM processed as a master. It seems that the only necessary full AXI port to support bursts is the ID (aside from burst length and size, of course).

I could safely synthsize and run an AXI bus without Lock, Cache, Protection, Region, and QoS ports.

 

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