02-13-2018 06:55 AM
Can someone point me at the best docs to read to mix hand coded VHDL with IP block designs?
I'm exploring vivado to see how it all hangs together -
What I'm trying to do is a simple mix by loading a half adder from a VHDL file
and connect it to a simple clock wizard output. (no reason - I'm just trying to keep it simple)
I can load the VHDL no problem and create the clock from IP but can't yet see how
to wire it up.
02-13-2018 07:39 AM
I can load the VHDL no problem and create the clock from IP but can't yet see how to wire it up.
Expose all the ports of an IP, use it as a module.
Write a top level wrapper in which you hand instantiate and connect the IP blocks and your self-written VHDl/Verilog modules.
02-14-2018 03:50 AM
I'm not sure how to do this yet - I'm not clear about much in Vivado as yet.
(what a module is - when wrappers are needed - exposing IP ports are all new
to me so far - give me another week ... )
What I have made work is to package up my (now) full adder as an IP
and start the design that way (IE write some VHDL - turn it into an IP and use it)
I have a black box issue but at least I moved on and learned some new things.
I expect your solution is the correct one which I'll come back to when I understand more.
I would have thought there would be a tutorial for connecting hand coding to IP somewhere?
I haven't found one though.
02-14-2018 01:49 PM
Inserting Vivado IP into your project is the same as inserting one VHDL component into another VHDL component. That is, you simply declare it and instantiate it.
How do you declare/instantiate IP? Well, the "Instantiation Template" that comes with the IP tells all. In the screen-shot below from Vivado v2017.3, you will see I have a clock-module IP called CLK_GEN2. One of the folders under CLK_GEN2 is is called "Instantiation Template" and inside this folder is a text file called CLK_GEN2.vho. Just double click the .vho file in your project and it will open and tell you everything about declaring/instantiating the IP.