06-11-2019 02:39 PM
What is the correct way to take an existing Xilinx IP core (xdma in this case), and modify the HDL while also adding a new IP block (from the IP Catalog) to the core?
1) I followed the steps in Appendix D of UG896 (Editing Subsystem IP):
set_param project.defaultIPCacheSetting none
<Generate files using OOC flow>
set_property IS_LOCKED true [get_files xdma_0.xci]
<Edit HDL to make changes>
launch_runs -jobs 8 xdma_0_synth_1
<Generate a bitstream at my project level>
This works if I make minor edits to the HDL files. It fails when I try to add a new IP block to the core. The newly instantiated IP block does not resolve. Adding that IP block at my project level doesn't help. Unless I've missed it, UG896 doesn't seem to address this use case.
2) UG1118 p20 (Editing an Existing Custom IP) describes a way to edit and repackage IP, but it doesn't seem to work for
Xilinx IP, only custom IP. Is there a way I can 'copy' the Xilinx IP to make it Custom IP, and then edit the non-encrypted parts of it?
3) I tried creating a new project, copying the XCI and modified files from sources/ip/xdma_0 directory and then
exporting that using Create and Package New IP. That didn't work either: OOC synthesis fails with "Error generated from encrypted envelope." Also the Customize IP editor results in a completely blank page.
4) I realize that my sources/ip/xdma_0 directory requires the addition of a new ip_3 subdir, containing the .xci file for my new core. And somehow the xdma_0.xci file must be told to use that new ip_3 subdir. I just don't know how to make that happen.
Any advice on how to proceed?
06-17-2019 04:00 AM
can you try the following and then let us know if it worked
1. Disable IP cache in the project (select disabled in the project settings) see attached scrennshot
2. add the IP's to the design
3. Follow the procedure of editing subsystems IP
06-17-2019 09:13 AM
Thanks for your response Suraj. I tried that, but it is not enough.
The new IP is included in my project, but the instantiation is not resolved inside of the Xilinx OOC IP core. Inside of the Xilinx IP core hierarchy, the module is displayed with a question mark icon. Something like this: MyInstanceName: xil_defaultlib.XilinxIPName
The same IP instantiated in my top level module is resolved properly.
How do I include this IP inside the Xilinx IP core hierarchy?