Flow: I am using Windows 10, the Vivado flow, version 2019.2.1_AR73052_AR72954. Our target board is an Alveo U200.
Task: For our design, we need to insert a simple multiplexer inside of the xilinx xdma module. We would like to insert this multiplexer just before the PCIe physical layer to allow the choice between tlp packets sent through the standard xdma module ports and hardcoded tlp packets that we have written ourselves. To clarify, our multiplexer will have 1 select input and 4 data inputs, with 2 of the data inputs tied to the xdma's internal pci_exp_txn and pcie_exp_txp wires. We would like the other 2 data input wires, as well as the select input wire, to propagate up through the xdma's internal wrappers to the surface. This would prevent us from being forced to generate our select and tlp packet logic inside of the xdma itself.
Flow > Create Block Design
Add PCIe component with x8 lanes to the block design.
Add DDR4 component to the block design.
Run block automation and enable the PCIe AXI Master Slave Interface.
Run connection automation on all listed connections.
Validate and save the block design.
Create an HDL wrapper for the block design.
Synthesize the project.
Attempts: With these steps followed, we first attempted setting the IS_LOCKED property of the XDMA module to TRUE using the tcl console. This allowed us to view the internal verilog of the XDMA module and modify its functionality with Sublime Text. However, upon trying to synthesize the project, the synthesis tool would use the cached IP results from the previous synthesis and ignore any changes that had been made.
In an attempt to try and subvert this, I cleared the IP cache in the Vivado GUI through Tools > Settings > IP > Clear IP Cache, set the project cache property to none and then attempted to synthesize the project again. This resulted in many errors from the synthesis trying to use the IP Cache results when there were none. In the Design Runs tab, I could see that the XDMA module was not synthesizing either, indicating that it had been locked by the user.
After this attempt, I closed the project and created a new project following the first 7 steps above identically. Before step 8, the first synthesis, I noticed that I now had access to the verilog code for every module with none of the modules being locked in this project. I accepted this as beneficial and tried to synthesize the design. I let it run for approximately 2 hours. The previous project's synthesis had run in 45 minutes or so. Every module synthesized except the XDMA module. This module hung indefinitely with no apparent progress. I attempted closing the project and reopening it. I also tried rebooting my pc and synthesizing, but this also did not work. After these 2 attempts, I deleted both the project folders and rebooted my pc.
Currently: I followed the same 8 steps above, and have managed to synthesize a project in which none of the Xilinx modules are locked, but all of the verilog code is visible. I do not know how, which is why I've detailed it so precisely in the case that it is a bug. With that accomplished, I again edited the various XDMA internals to add our minimal logic and propagate up the 3 wires we need. Unfortunately if I synthesize this project all of my changes are erased and the modules revert to their original states or the cached IP results from the first synthesis are used.
How can I keep these internal edits permanently without them being overwritten during synthesis?
How can I force a module to synthesize without using the cached IP results?
How can I force the block design GUI to update with the changes that have been made to the IP's verilog?