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Registered: ‎06-24-2019

Module references are out-of-date when add RTL module in BD



I am using Artix-7 FPGA, and I use the 2018.3 vivado version.

I followed UG994 to add a RTL module in my block design. Below are the steps,

  1. Add the source file into the project
  2. Open the Block Design, and choose Add Module in right-click menu, and choose the Verilog source file. Then a RTL block is added in the BD successfully.
  3. Do the connection between the RTL block and other IP modules.
  4. Generate Output Products via OOC per Block Design
  5. Run Synthesis

After synthesis, I found on the top of GUI there is a yellow bar with a warning like the below picture,

Screen Shot 2019-10-11 at 3.36.29 PM.png

I am not sure if this warning can be ignored.

When I click the refresh, and after generating the BD, this warning appears again.

I run the report_ip_status in tcl console, and it showed the RTL referenced module as below,

Screen Shot 2019-10-11 at 3.42.58 PM.png

I upgrade the module in IP status while the warning exited all the same.

Every time I run the synthesis, the BD will be generated again which takes a lot of time.

I have already create a HDL wrapper, but the HDL wrapper was generated when I generate the BD OOC, isn’t it?

And I also instantiated the wrapper in top verilog file.

Could you help to check my steps if something wrong or I missed? Or could you give some suggestion on solving it?

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Xilinx Employee
Xilinx Employee
Registered: ‎05-22-2018

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