Moving median filter code

[kp1998_]

Hello

I have written the following moving median filter code  - 

module median_filter_main(clk,A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,window,med);
input [7:0]A0,A1,A2,A3,A4,A5,A6,A7,A8,A9;
input [3:0]window;
input clk;
reg [7:0]max,min;
output reg[7:0]med;
integer i,j,k;
reg [7:0]temp;
reg [7:0]arr[0:9];
reg [7:0]array[0:9];
reg [7:0]dat0,dat1,dat2,dat3,dat4,dat5,dat6,dat7,dat8,dat9;
always @(posedge clk)
begin
dat0 <= A0;
dat1 <= A1;
dat2 <= A2;
dat3 <= A3;
dat4 <= A4;
dat5 <= A5;
dat6 <= A6;
dat7 <= A7;
dat8 <= A8;
dat9 <= A9;
end
always@*
begin
array[0] = dat0;
array[1] = dat1;
array[2] = dat2;
array[3] = dat3;
array[4] = dat4;
array[5] = dat5;
array[6] = dat6;
array[7] = dat7;
array[8] = dat8;
array[9] = dat9;
for (i = 10; i > 0; i = i - 1) begin
for (j = 0 ; j < i; j = j + 1) begin
if (array[j] > array[j + 1])
begin
temp = array[j];
array[j] = array[j + 1];
array[j + 1] = temp;
end
end
end
end
always @(posedge clk)
begin
arr[0] <= array[0];
arr[1] <= array[1];
arr[2] <= array[2];
arr[3] <= array[3];
arr[4] <= array[4];
arr[5] <= array[5];
arr[6] <= array[6];
arr[7] <= array[7];
arr[8] <= array[8];
arr[9] <= array[9];
end
always@*
begin
for(k=0;k<10;k=k+1)
begin
if((k-window)>k)
assign max=k;
if((k+window)<50)
assign min=(k+window)-1;
assign arr[k]=arr[(max+min)/2];
assign med=arr[k];
end
end
endmodule

I am getting an error as - bit-select or part-select is not allowed in a assign statement for non-net arr for this line in the code - assign arr[k]=arr[(max+min)/2];

and now If i declare array arr as wire then i am getting an error as -  procedural assignment to a non-register arr is not permitted, left-hand side should be reg/integer/time/genvar 

for these lines - 

arr[0] <= array[0];
arr[1] <= array[1];
arr[2] <= array[2];
arr[3] <= array[3];
arr[4] <= array[4];
arr[5] <= array[5];
arr[6] <= array[6];
arr[7] <= array[7];
arr[8] <= array[8];
arr[9] <= array[9];

So how to declare array arr in the code as a reg or wire and how to avoid the errors coming because these declarations.

Please help with this. Waiting for your reply at the earliest.

Regards

Thank you

[rshekhaw · Accepted solution]

Hi @kp1998_ ,

Assign inside an always block is the procedural assignment. It is not synthesizable and should not be used.

Continous assignment, or assign outside the always block is there for connecting nets and used

all over the places. LHS of such an assignment must be a net type. it cannot be a reg.

On the other hand all LHS in always blocks must be of 'reg' type.

Thanks,

Raj

[kp1998_]

Thank you
Can u please verify whether the code is correct or not interms of functionality, i am not getting proper output. if u could the code and let me know will be of great help.

[drjohnsmith]

So what have u tried to state not getting correct output.
What's the test look like ?

[dgisselq]

@kp1998_,

This design does not work.

Even if it would work (and it won't), if you cannot tell if your design works or not, then it does not really work.

Why is this so?  Because everything needs to be maintained at some time, and asking someone external to verify your code every time you make a change isn't really a sustainable business model.

Personally, this is not how I would approach this problem.  Sorting 10 8-bit numbers in a single clock cycle is going to force you into a slower clock rate, since very few other operations you might do will require this.  How exactly I would approach the problem, though, would be system context dependent.  Questions I'd ask first include things like 1) how fast is your data arriving?  2) How often does the median filter need to produce an answer?  3) Are approximate answers "good enough", and so on.

Dan

[kp1998_]

Hello

I am currently working with 10 inputs and will later increase the number of inputs to 500.

So is it better to consider the inputs together.

The median filter should produce a result everytime the window moves towards the right.

And yah approximate result is fine.

Could u suggest some way to correct the code as this not correct.

Would be great help 

Thank you

[drjohnsmith]

So what have u tried to make statement not getting correct output.
What's the test look like ?

Or is this home work and you want some one to do it for you ?

[dgisselq]

To operate on faster data, at a high clock rate ...

1. Pick a fixed block size, pick a threshold
2. Count the number of data points that are above the threshold
3. If the number of data points above the threshold is greater than 50%, raise the threshold.  If lower (or sometimes just if otherwise), lower the threshold

This works great on high speed signals where you can afford whatever time it takes for the operator to converge.

Dan