03-11-2020 02:20 PM
Hello, I am trying to develop an Block Design that will support four SPI interfaces. The FPGA will be Slave for all four SPI devices. Here is my concept:
I am using the four AXI QUAD SPI v3.3 IPs and will need to configure each for Standard Mode. Each SPI IP will be connected to the PS_Side over AXI bus.
The problem is in the IP Integrator I can't connected the MISO lines together, how can this be done?
03-11-2020 02:47 PM
This is what I have so far:
I am connecting the MOSI to io0_i port and MISO to io0_o port according to page 20 of PG153. However, I think there must typo or I don't understand why but I think io0_o should be MISO in the document.
Why can't I tied all the MISO lines together?
03-11-2020 03:00 PM
Check table 2-2. IO0 is MOSI. IO1 is MISO. But either way there is an input path and output path on those blocks. You cannot have multiple outputs driving one signal.
03-11-2020 03:10 PM
Hello, thanks for responding to my message. I guess I will need to add in some control logic. I'll invert each of the Chip Selects (CSx) and then connect them into a CONCAT IP and then connect up to a MUX and then connected each MISO pin of the SPI IP into the MUX. I just need to find a MUX IP now.
03-11-2020 03:23 PM
Hello, thanks for responding to my message. Table 2-2 is a little confusing. I don't get the io0 and io1 ports. I thought io1 would be in dual mode. Let me run this by you:
Is the image correct for a Slave Configuration: io0_o is MOSI and io1_i is MISO?
Sorry for being so slow here.
Thank you very much,
03-11-2020 08:20 PM
Thanks, just to be sure and correct me if I'm wrong here.
Is this correct?
io0_o is MOSI
io1_i is MISO
Now I need to connect io0_o to an In port and io1_i to an Out port is that correct?
03-11-2020 11:28 PM
Yes to the first part, no to the second part. The pin is bidirectional. The other side could be a master or slave on the same line. So you must connect it to a IOBUF primitive on one pin. It is a bidirectional interface. But only and input or output at any given time.
03-12-2020 06:35 AM
Hello, thanks for responding to my post. In this case the SPI_DIN and SPI_DOUT are connected to only one device, a TI DSP that has 4 Chips Selects. In this case no one will be driving the SPI_DOUT pin. Is this okay?
If the situation was different, is this how you want it connected:
03-12-2020 12:16 PM
No, the IOBUF should be connected like this:
Of course this depends on the type of memory you are using. Not all memory parts behave this way. You will see it exactly this way on designs like for the AC701 which has a SDI flash on it and the pins connect to it via a bidi signal. But I don't know what you are connecting to so I am not sure how to advise here.
03-12-2020 01:23 PM
Hello, thanks for responding to my post. Here is my setup:
I may have caused some confusion. In my application the SPI_DOUT from the FPGA is only connected to the DSP so I only need to tie the io1_o pin to an OUT port.
I may have given you the impression that I was connected to many devices.
Does this sound okay?
03-12-2020 01:51 PM
Got it, so you can can't connect all your io0_0 pins together in the FPGA. You will need to have 4 pins out of the FPGA but you can connect them together on the board.
03-12-2020 02:12 PM
In the FPGA I added four SPI blocks and set them as Slaves. I connected the SPI_DIN to each IP blocks. Each IP Block was connected to one CSx pin. I also then run the Chip Selected through a NOT Gate and then through a CONCAT IP and then into an RTL Mux block that is used to select which IP block will drive the SPI_DOUT line.
This should work.
03-12-2020 02:56 PM
Thanks for helping do what is right.
So are you saying to use IOBUF for all FPGA outputs?
In this case the SPI_DOUT should go to a IOBUF.
03-12-2020 03:14 PM
No. I answered this before. Use the IOBUF directly connected to the SPI pins then out to the FPGA. Just drive the SPI0 pins in IPI directly out to the top. Then create the top level HDL wrapper which makes the IOBUF for you.
03-12-2020 03:52 PM
03-12-2020 04:52 PM
Nope. Don;t insert the IOBUF in IPI. Just make SPI_0 external in IPI.
The entire IO0 goes to one BUFIO. The entire IO1 goes to another IOBUF. The HDL wrapper will do this for you.
Look at the SPI example design to see the connectivity if needed. It is done in RTL but the connections are the same.
03-12-2020 06:47 PM
Quick question. I like having the IPI has my top level wrapper and would like to place the IOBUF in the IPI is that still okay? I like doing everything in the IPI. Is that still okay? Maybe it's because I'm still learning Vivado and how things are done.
I'm looking a the SPI example and see what you were trying to get me to understand. I'm looking at its RTL schematic.
Thank you very much.
03-12-2020 08:00 PM
Well, I think I'm getting closer:
I'm so thankful for your help. I would have never figured to connect an IOBUF to the SPI IP. Please let me know if I'm getting closer.
03-13-2020 09:27 AM
Hello, thank you for sticking with me while I got this worked out. What is the SS signal? I have the clock, the SPI_Select, MOSI and MISO.
03-13-2020 10:31 AM
Hello, in my image the SS is what I am calling SPI_SELECT which is going into a Utility Buffer BUFG_I and out on BUFG_O and in to the IP on port spisel. Is this okay? Is it really necessary to go through a Buffer? Won't the buffer automatically be inferred?