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Scholar
Scholar
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Registered: ‎12-07-2018

Multi Slave Standard SPI

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Hello, I am trying to develop an Block Design that will support four SPI interfaces. The FPGA will be Slave for all four SPI devices. Here is my concept:

SPI.jpg

I am using the four AXI QUAD SPI v3.3 IPs and will need to configure each for Standard Mode. Each SPI IP will be connected to the PS_Side over AXI bus.

The problem is in the IP Integrator I can't connected the MISO lines together, how can this be done?

Thanks,

Joe

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

You need IOBUF on MOSI, MISO, and SCLK.   Not the SPISEL.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

That would be a multiple driver which is not allowed.  You can't connect multiple output pins to a single pin.

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Scholar
Scholar
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Registered: ‎12-07-2018

This is what I have so far:

Mult_slave_spi.jpgip.jpg

 

I am connecting the MOSI to io0_i port and MISO to io0_o port according to page 20 of PG153. However, I think there must typo or I don't understand why but I think io0_o should be MISO in the document. 

Why can't I tied all the MISO lines together?

Thank you,

Joe

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

Check table 2-2.  IO0 is MOSI.  IO1 is MISO.  But either way there is an input path and output path on those blocks.  You cannot have multiple outputs driving one signal.  

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Scholar
Scholar
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Hello, thanks for responding to my message. I guess I will need to add in some control logic. I'll invert each of the Chip Selects (CSx) and then connect them into a CONCAT IP and then connect up to a MUX and then connected each MISO pin of the SPI IP into the MUX. I just need to find a MUX IP now. 

Joe

 

 

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, thanks for responding to my message. Table 2-2 is a little confusing. I don't get the io0 and io1 ports. I thought io1 would be in dual mode. Let me run this by you:

spi_io.gif

Is the image correct for a Slave Configuration: io0_o is MOSI and io1_i is MISO?

Sorry for being so slow here.

Thank you very much,

Joe

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Scholar
Scholar
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Registered: ‎12-07-2018

Oops, my image is incorrect:

spi_io.gif

io0_o is MOSI

io1_i is MISO

Now I'm looking for a generic MUX ip.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

There is an I and O because those are bidirectional pins.  You are supported to connect them up to a IOBUF.

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Scholar
Scholar
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Registered: ‎12-07-2018

Thanks, just to be sure and correct me if I'm wrong here.

Is this correct?

io0_o is MOSI

io1_i is MISO

Now I need to connect io0_o to an In port and io1_i to an Out port is that correct?

Thank you,

Joe

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

Yes to the first part, no to the second part.  The pin is bidirectional.  The other side could be a master or slave on the same line.  So you must connect it to a IOBUF primitive on one pin.  It is a bidirectional interface.  But only and input or output at any given time.

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, thanks for responding to my post. In this case the SPI_DIN and SPI_DOUT are connected to only one device, a TI DSP that has 4 Chips Selects. In this case no one will be driving the SPI_DOUT pin. Is this okay?

 

If the situation was different, is this how you want it connected:

SPI_DOUT.gif

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

No, the IOBUF should be connected like this:

IOBUF qspi_iobuf
(.I(io0_o),
.IO(io0_io_pad),
.O(io0_i),
.T(io0_t));

Of course this depends on the type of memory you are using.  Not all memory parts behave this way.  You will see it exactly this way on designs like for the AC701 which has a SDI flash on it and the pins connect to it via a bidi signal.  But I don't know what you are connecting to so I am not sure how to advise here.

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, thanks for responding to my post. Here is my setup:

SPI_conn.gif

 

DSP_SPI.jpg

DSP_pin.gif

I may have caused some confusion. In my application the SPI_DOUT from the FPGA is only connected to the DSP so I only need to tie the io1_o pin to an OUT port.

I may have given you the impression that I was connected to many devices. 

Does this sound okay?

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

Got it, so you can can't connect all your io0_0 pins together in the FPGA.  You will need to have 4 pins out of the FPGA but you can connect them together on the board.

 

 

multislavespi.jpg
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Scholar
Scholar
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In the FPGA I added four SPI blocks and set them as Slaves. I connected the SPI_DIN to each IP blocks. Each IP Block was connected to one CSx pin. I also then run the Chip Selected through a NOT Gate and then through a CONCAT IP and then into an RTL Mux block that is used to select which IP block will drive the SPI_DOUT line.

SPI.gif

This should work.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

No still use the IOBUF.  io0 is MOSI,  io1 is MISO.  Use IOBUFs to protect the FPGA pins.

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Scholar
Scholar
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Registered: ‎12-07-2018

Thanks for helping do what is right.

So are you saying to use IOBUF for all FPGA outputs?

In this case the SPI_DOUT should go to a IOBUF.

spi.jpg

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

No.  I answered this before.  Use the IOBUF directly connected to the SPI pins then out to the FPGA.  Just drive the SPI0 pins in IPI directly out to the top.  Then create the top level HDL wrapper which makes the IOBUF for you.

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Scholar
Scholar
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Okay, I'm an idiot, can you please look at this. I know it must be wrong. I'll upload the tcl so you can regenerate this SPI example.

SPI_EXAMPLE.jpg

Sorry for being so slow and thank you for help. 

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Scholar
Scholar
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Registered: ‎12-07-2018

Okay, here's another try:

SPI_EXAMPLE.jpg

I should stick with the terms MOSI and MISO. 

Thanks for your help.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

Nope.  Don;t insert the IOBUF in IPI.  Just make SPI_0 external in IPI.

The entire IO0 goes to one BUFIO.  The entire IO1 goes to another IOBUF.  The HDL wrapper will do this for you.

Look at the SPI example design to see the connectivity if needed.  It is done in RTL but the connections are the same.

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Scholar
Scholar
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Will do. thank you very much.

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Scholar
Scholar
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What is IPI?

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Xilinx Employee
Xilinx Employee
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IPI is IP Integrator or the block design.

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Scholar
Scholar
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Registered: ‎12-07-2018

Quick question. I like having the IPI has my top level wrapper and would like to place the IOBUF in the IPI is that still okay? I like doing everything in the IPI. Is that still okay? Maybe it's because I'm still learning Vivado and how things are done.

I'm looking a the SPI example and see what you were trying to get me to understand. I'm looking at its RTL schematic.

Thank you very much.

Joe

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Scholar
Scholar
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Well, I think I'm getting closer:

SPI.jpg

I'm so thankful for your help. I would have never figured to connect an IOBUF to the SPI IP. Please let me know if I'm getting closer.

Respectfully,

Joe

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

Yes you have it right now.  Just connect the SS signals and you look done to me.

 

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, thank you for sticking with me while I got this worked out. What is the SS signal?  I have the clock, the SPI_Select, MOSI and MISO. 

 

Respectfully,

Joe

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-01-2007

SS is the slave select pins.

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Scholar
Scholar
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Hello, in my image the SS is what I am calling SPI_SELECT which is going into a Utility Buffer BUFG_I and out on BUFG_O and in to the IP on port spisel. Is this okay? Is it really necessary to go through a Buffer? Won't the buffer automatically be inferred?

 

Respectfully,

Joe

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