10-12-2011 03:25 AM
As I started my design with a top level schematic I did not know that sheet size could play a matter.
The automatically created symbols (from VHDL files) were large and I could not find possibilities to shrink the default font size and so on.
So with growing design I had to choose a larger and larger sheet size and now A0 (nothing greater to select) ends this procedure, but my design is not finshed yet.
Is there a possibility to shrink the generated symbols, e.g. by setting preferences anywhere in ISE?
I don't want to use -> edit symbol and so on, for every created symbol after creation.
Is it possible to distribute the design on multiple sheets and connect them by "ports or sheet connectors" like in PCB design programms (Altium) together, so that a top level schematic consists on multiple schematics?
10-13-2011 12:27 AM
yes, hierarchical design is no problem for the ISE Schematic tool.
Just break your design in useful subgroups and create a schematic for each.
Then you can use the Create Schematic Symbol tool from the Design Utilities.
The symbols are available then in a local library, appearing in the schematic tool after reopening it (all former schematic windows need to be closed first!)
Then you can place all these symbols in the new top-level schematic and wire them up.
Of course this can be done over more than two levels of hierarchy and functional blocks that you use more often can have multiple instances of the same schematic. ISE canb handle that.
Only thing that is missing is a hierarchical push/pop option e.g as known from Simulink subsystems or other 3rd party tools which allow dynamic creation of hierarchies. (don't mistake it with the viewing push/pop option)
Have a nice synthesis